Integrated circuit with reduced signaling interface
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
Claims15
An integrated circuit comprising:
- (a) a test clock (TCK) input;
- (b) a first die coupled to the TCK input, the first die including a first state machine coupled to the TCK input;
- and
- (c) a second die stacked vertically on the first die, the second die coupled to the TCK input, the second die including a second state machine coupled to the TCK input.
Dependencies are inferred from the claim text.