Leakage screening based on use-case power prediction
AssigneeGoogle Inc.
InventorsEmre Tuncer, Kaushik Balamukundhan, Yiran Li
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Abstract
This document describes techniques and systems for leakage screening based on power prediction. In particular, the described systems and techniques estimate, during a silicon manufacturing process, use-case power (e.g., low power, ambient power, high power, gaming power) to apply leakage screening for apart (e.g., a chip package). In some aspects, measurable silicon parameters (e.g., leakage values, bin values, processor sensor values) may be used for use-case power prediction. Using the described techniques, a maximum allowable predicted use-case power can be determined and used for leakage screening regardless of an individual rail leakage or voltage bin assignment.
Claims7
A method for leakage screening based on power prediction, the method comprising:
- receiving a chip package that has been wafer-tested, die-cut, packaged, and binned, the chip package having a plurality of rails, each rail of the plurality of rails assigned to a corresponding voltage bin of a plurality of voltage bins based on an adaptive supply voltage value;
- obtaining one or more silicon parameters associated with the chip package, the one or more silicon parameters determined during wafer-level testing of the chip package and including at least a leakage current value for each rail;
- performing a multi-rail test on the plurality of rails of the chip package to provide per-rail results across the plurality of voltage bins, each rail of the plurality of rails tested based on a corresponding leakage current value and the adaptive supply voltage value of the corresponding voltage bin;
- determining, based on an aggregate of the per-rail results across the plurality of voltage bins, an aggregate value;
- and
- categorizing the chip package based on the aggregate value.
Dependencies are inferred from the claim text.