Test circuit and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsieh-Hung Hsieh, Yen-Jen Chen, Tzu-Jin Yeh
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Abstract
An IC includes a plurality of pads at a top surface of a semiconductor wafer, an amplifier configured to receive a first AC signal at an input terminal, and output a second AC signal at an output terminal, a first detection circuit coupled to the input terminal and configured to output a first DC voltage to a first pad of the plurality of pads responsive to the first AC signal, and a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal.
Claims20
An integrated circuit (IC) comprising:
- a plurality of pads at a top surface of a semiconductor wafer;
- an amplifier configured to receive a first alternating current (AC) signal at an input terminal, and output a second AC signal at an output terminal;
- a first detection circuit coupled to the input terminal and configured to output a first direct current (DC) voltage to a first pad of the plurality of pads responsive to the first AC signal;
- and
- a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal.
An integrated circuit (IC) comprising:
- a plurality of pads at a top surface of a semiconductor wafer;
- an amplifier configured to receive a first alternating current (AC) signal at an input terminal, and output a second AC signal at an output terminal;
- a first detection circuit coupled to the input terminal and configured to output a first direct current (DC) voltage to a first pad of the plurality of pads responsive to the first AC signal;
- and
- a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal,
- wherein each of the amplifier and the first and second detection circuits is configured to have a gain controllable based on one or more voltage levels received at the plurality of pads.
A method of testing an integrated current (IC), the method comprising:
- electrically accessing a pad array at a top surface of a semiconductor wafer;
- receiving a first alternating current (AC) signal at an input terminal of an amplifier of the IC;
- outputting a second AC signal at an output terminal of the amplifier;
- in response to the first AC signal, using a first detection circuit of the IC to output a first direct current (DC) voltage to a first pad of the pad array;
- and
- in response to the second AC signal, using a second detection circuit of the IC to output a second DC voltage to a second pad of the pad array.
Dependencies are inferred from the claim text.