Managing power in an integrated circuit for high-speed activation

A vehicle comprising:

• one or more electronically controllable devices;
• a controller configured to manage power consumed by an integrated circuit in the controller during a high-speed activation time interval, the controller being configured to control at least one of the electronically controllable devices in the vehicle in response to receiving an activation signal, the controller including:
• two or more processor cores disposed on the integrated circuit the two or more processor cores being configured to use an amount of power lower than a nominal power limit during normal operation,
• a storage module for storing code executable by two or more of the processor cores, and
• an overdrive manager configured to cause at least a portion of the stored code to be executed by a first subset of fewer than all of the processor cores at a first power level, the first power level exceeding the nominal power limit, during the high-speed activation time interval to boot functionality on the first subset for controlling an electronically controllable device in a first subsystem of the vehicle, and at least a portion of the stored code to be executed by a second subset of one or more of the processor cores at a second power level lower than the first power level at least during the high-speed activation time interval to boot functionality on the second subset for controlling an electronically controllable device in a second subsystem of the vehicle different from the first subsystem of the vehicle;
• and
• an activation port configured to provide the activation signal for activating control of at least one of the electronically controllable devices by the controller.