Bi-layer metal electrode for micromachined ultrasonic transducer devices

A method of forming an ultrasonic transducer device, the method comprising:

• forming a bi-metal transducer lower electrode layer over a complementary metal oxide semiconductor (CMOS) substrate, the lower electrode layer comprising a titanium (Ti) layer of 100 nanometers (nm) to 300 nm formed on the CMOS substrate and a ruthenium (Ru) layer of 10 nm to 30 nm formed on the Ti layer;
• etching the bi-metal transducer lower electrode layer to form a patterned metal electrode layer;
• forming an SiO2 insulation layer of 400 nm to 900 nm over the patterned metal electrode layer;
• planarizing the SiO2 insulation layer to the Ru layer, wherein the Ru layer serves as a chemical mechanical polishing (CMP) stop layer that has CMP selectivity with respect to the SiO2 and the Ti layer;
• forming a bottom cavity layer over the between the patterned metal electrode layer, the bottom cavity layer comprising a chemical vapor deposition (CVD) SiO2 layer having a thickness of 10 nm to 30 nm and an atomic layer deposition (ALD) Al2O3 layer having a thickness of 20 nm to 40 nm formed on the SiO2 layer;
• forming a membrane support layer over the bottom cavity layer, the membrane support layer comprising an SiO2 layer having a thickness of 100 nm to 300 nm;
• etching a cavity in the membrane support layer;
• and
• bonding a membrane to the membrane support layer to seal the cavity, the membrane comprising doped silicon having a thickness of 2 microns (μm) to 10 μm,
• wherein the Ru layer has a CMP removal rate of 100 times to 200 times slower than that of the SiO2 insulation layer.

An ultrasonic transducer device, comprising:

• a patterned metal electrode layer disposed on first regions of a substrate, the patterned metal electrode layer comprising a lower layer and an upper layer formed on the lower layer;
• a planarized insulation layer disposed on second regions of the substrate layer, wherein the upper layer comprises an electrically conductive material that has CMP selectivity with respect to the insulation layer and the lower layer, and wherein the upper layer has a CMP removal rate slower than that of the insulation layer;
• a cavity defined in a membrane support layer, the membrane support layer formed over the patterned metal electrode layer and the planarized insulation layer;
• and
• a membrane bonded to the membrane support layer,
• wherein the upper layer has a CMP removal rate of about 100 times to about 200 times slower than that of the insulation layer.

An ultrasonic transducer device, comprising:

• a patterned bi-metal transducer lower electrode layer formed on first regions of a complementary metal oxide semiconductor (CMOS) substrate, the lower electrode layer comprising a titanium (Ti) layer of 100 nanometers (nm) to 300 nm formed on the first regions of the CMOS substrate and a ruthenium (Ru) layer of 10 nm to 30 nm formed on the Ti layer;
• a planarized SiO2 insulation layer of 400 nm to 900 nm formed on second regions of the CMOS substrate, wherein the Ru layer serves as a chemical mechanical polishing (CMP) stop layer that has CMP selectivity with respect to the SiO2 and the Ti layer;
• a bottom cavity layer formed over the between the patterned metal electrode layer, the bottom cavity layer comprising a chemical vapor deposition (CVD) SiO2 layer having a thickness of 10 nm to 30 nm and an atomic layer deposition (ALD) Al2O3 layer having a thickness of 20 nm to 40 nm formed on the SiO2 layer;
• a membrane support layer formed over the bottom cavity layer, the membrane support layer comprising an SiO2 layer having a thickness of 100 nm to 300 nm;
• a cavity defined in the membrane support layer;
• and
• a membrane bonded to the membrane support layer to seal the cavity, the membrane comprising doped silicon having a thickness of 2 microns (μm) to 10 μm,
• wherein the Ru layer has a CMP removal rate of 100 times to 200 times slower than that of the SiO2 insulation layer.