Watchdog for addressing deadlocked states
AssigneeInfineon Technologies AG
InventorsStephan Leisenheimer, Christof Bodner, Benjamin Kollmitzer, Richard Heinz
Life of this patent
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Abstract
The described techniques address deadlocking issues associated with interconnected hardware devices that share bus lines associated with a digital communication interface. A watchdog-based solution is described that may be implemented internally within the interconnected hardware devices or, alternatively, as an external component. The watchdog circuity may monitor a logic state of one or more internal connections of a hardware device and cause one or more portions of the hardware device to reset when a deadlock condition is detected using this internal monitoring.
Claims22
A device, comprising:
- a transistor coupled to a bus line external to the device and to logic circuitry internal to the device, the transistor being configured to change a logic state of the bus line from a first logic state to a second logic state in response to an assertion of a control signal by the logic circuitry;
- and
- watchdog circuitry internal to the device, the watchdog circuitry being configured to provide an overtime signal to the logic circuitry when the control signal remains asserted at the same logic state in excess of a threshold timeout period.
A system, comprising:
- a first device configured to selectively drive a bus line;
- and
- a second device coupled to the first device via the bus line, the second device being configured to selectively drive the bus line and including:
- a transistor coupled to the bus line and to logic circuitry internal to the second device, the transistor being configured to change a logic state of the bus line from a first logic state to a second logic state in response to an assertion of a control signal by the logic circuitry indicating that the second device is to drive the bus line;
- and
- watchdog circuitry internal to the second device, the watchdog circuitry being configured to monitor a logic state of the control signal, and to provide an overtime signal to the logic circuitry when the control signal remains asserted at the same logic state in excess of a threshold timeout period.
A method, comprising:
- changing, via a transistor, a logic state of a bus line from a first logic state to a second logic state in response to an assertion of a control signal by a logic circuitry internal to a first device, the transistor being coupled to (i) a bus line external to the first device, and (ii) the logic circuitry;
- and
- outputting, via watchdog circuitry internal to the first device, an overtime signal when the control signal remains asserted at the same logic state in excess of a threshold timeout period.
Dependencies are inferred from the claim text.