Method of testing electronic circuits and corresponding circuit
AssigneeSTMicroelectronics S.r.l.
InventorDavid Vincenzoni
Life of this patent
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Abstract
A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.
Claims20
A method for testing a circuit, the method comprising:
- collecting a sequence of N-bit digital test data of a test stimulus signal applied to an input node of the circuit;
- and
- applying a lossless compression to the N-bit digital test data to obtain R-bit compressed test data in parallel format over R output pins of the circuit, wherein R is less than N, wherein the testing comprises testing an integral non-linearity behavior or a differential non-linearity behavior of the circuit.
A method of testing an electronic circuit, the method comprising:
- receiving R-bit compressed test data from R output pins of the electronic circuit, where R is a real number;
- reconstructing N-bit digital test data from the R-bit compressed test data, wherein N is a real number greater than R;
- and
- performing the testing on the N-bit digital test data that was reconstructed from the R-bit compressed test data.
A circuit, comprising:
- compression circuitry configured to apply N-bit to R-bit lossless compression to N-bit digital test data to obtain therefrom R-bit compressed test data, wherein R is less than N;
- and
- a plurality of R output pins coupled to the compression circuitry to receive therefrom the R-bit compressed test data in parallel format.
Dependencies are inferred from the claim text.