Systems and methods for improving frequency response of a high-speed data acquisition device

A high-speed data acquisition device, comprising:

• a measurement circuit coupled to an input of the high-speed data acquisition device in a metering device, the metering device for use in a power system and configured to sample signals received at the high-speed data acquisition device input at a first sampling rate, the measurement circuit including an anti-aliasing filter implemented using a network of resistors and capacitors wherein the received input signals include signals received from one or more loads in the power system;
• an analog-to-digital converter (ADC) coupled to an output of the measurement circuit and configured to generate a digital data stream representative of the sampled input signals at an output thereof wherein the generated signals are indicative of one or more monitored parameters of the sampled signals;
• an interpolator responsive to the digital data stream to generate an interpolated digital signal with a higher sample rate than the first sampling rate;
• a selected response characteristic arbitrary magnitude finite impulse response (FIR) filter responsive to the interpolated digital signal to generate a filtered digital signal, the filtered digital signal used to correct for both the parasitic errors caused by the network of resistors and capacitors and the anti-aliasing filter response within the measurement circuit;
• and
• a decimator responsive to the filtered digital signal to reduce the sampling rate of the filtered digital signal and generate a decimated digital signal;
• providing the decimated digital signal for configuring one or more of the monitored parameters, and
• wherein the decimated signal indicates a power quality issue in the power system, and the controller is responsive by adjusting the one or more of the monitored parameters in the power system to reduce the effects of the power quality issue.