Wideband phase-locked loop for delay and jitter tracking

A system comprising:

• a receiver (RX) clock amplifier that amplifies an RX clock to generate an amplified RX clock;
• feed-forward clock circuitry coupled to the RX clock amplifier, the feed-forward clock circuitry comprising a first plurality of inverters that have a temperature-induced delay;
• and
• an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and a set of sampler circuits, the RX PLL to generate a multiphase, corrected RX clock and that comprises a phase interpolator, the phase interpolator comprising a second plurality of inverters having a negative delay that matches the temperature-induced delay of the first plurality of inverters.

A communication device comprising:

• feed-forward clock circuitry having a temperature-induced delay;
• and
• a phase-locked loop (PLL) coupled to the feed-forward clock circuitry, the PLL comprising:
• a phase interpolator positioned in a feedback path of the PLL and having a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry;
• a ring oscillator coupled to the phase interpolator;
• a pulse width modulation (PWM) current source to directly modulate current provided to the ring oscillator;
• and
• a phase detector to combine the clock with the feedback path from the ring oscillator.