Low-complexity inverse sinc for RF sampling transmitters

A system comprising:

• a first-stage up-sampler having a first sampler input and a first sampler output;
• a digital-to-analog converter (DAC) response compensator having a compensator input and a compensator output, the compensator input coupled to the first sampler output;
• a second-stage up-sampler having a second sampler input and a second sampler output, the second sampler input coupled to the compensator output;
• a digital up-conversion mixer having a first mixer input, a second mixer input, and a mixer output, the first mixer input coupled to the second sampler output;
• and
• a radio frequency (RF) sampling DAC having a DAC input and a DAC output, the DAC input coupled to the mixer output.

A circuit comprising:

• delay circuitry having a delay input and a delay output;
• a compensation filter having a filter input and a filter output, the filter input coupled to the delay input;
• filter parameter computation circuitry having a first computation input, a second computation input, and a computation output;
• a scaling mixer having a first mixer input, a second mixer input, and a mixer output, the first mixer input coupled to the computation output and the second mixer input coupled to the filter output;
• and
• an adder having a first adder input, a second adder input, and an adder output, the first adder input coupled to the mixer output and the second adder input coupled to the delay output.