Digital phase-locked loop circuit

A system comprising:

• a transmitter configured to provide a data stream based on a clock signal, the clock signal being generated by a digital phase-locked loop (PLL) circuit, the PLL circuit comprising:
• a switch configured to provide a reference input signal having a first frequency in response to the clock signal being provided by the PLL circuit, the clock signal having a second frequency that is greater than the first frequency;
• a comparator configured to provide a series of bits based on the reference input signal and a comparator reference signal;
• proportional accumulator circuits configured to provide during respective different time intervals a proportional bit based on a respective bit of the series of bits and a previously outputted proportional bit by a respective proportional accumulator circuit, the proportional bit having an instantaneous value and an average value;
• shift registers configured during the respective different time intervals to shift the respective bit of the series to provide a shifted bit;
• a cancellation circuit configured to output a filtered proportional bit during the respective different time intervals based on the proportional bit and the shifted bit to remove the average value from the proportional bit;
• and
• a digital controlled oscillator configured to provide the clock signal based at least on the respective filtered proportional bit with a similar frequency as the reference input signal.

A digital phase-locked loop (PLL) circuit comprising:

• a digital controlled oscillator (DCO) having an input and an output;
• a cancellation circuit having first and second inputs and an output, the output of the cancellation circuit coupled to the input of DCO;
• a switch having an input coupled to the output of the DCO and an output;
• a comparator having a first input coupled to the output of the switch, a second input coupled to the output of the DCO, and an output;
• proportional accumulator circuits having respective first inputs coupled to the output of the comparator, respective second inputs coupled to respective outputs of a frequency synthesizer circuit, and respective outputs coupled to the first input of the cancellation circuit;
• and
• shift registers having respective first inputs coupled to the respective outputs of the frequency synthesizer circuit, respective second inputs coupled to the output of the comparator, and respective outputs coupled to the second input of the cancellation circuit.