Hybrid synchronous and asynchronous control for scan-based testing
AssigneeXilinx, Inc.
InventorsAlbert Shih-Huai Lin, Rambabu Nerukonda, Niravkumar Patel, Amitava Majumdar
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Abstract
An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.
Claims20
An integrated circuit, comprising:
- a first intellectual property core;
- first scan data pipeline circuitry configured to convey scan data to the first intellectual property core;
- first scan control pipeline circuitry configured to convey one or more scan control signals to the first intellectual property core;
- and
- a first wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock as provided to the first intellectual property core for a selected number of clock cycles.
An integrated circuit, comprising:
- an intellectual property core;
- and
- a wave shaping circuit adapted for scan testing the intellectual property core;
- wherein the wave shaping circuit includes:
- one or more wave shaping sub-circuits, wherein each wave shaping sub-circuit is operative to suppress a scan clock as provided to the intellectual property core in response to detecting a trigger event on an associated scan control signal;
- and
- each wave shaping sub-circuit is independently programmable to suppress the scan clock for a selected number of clock cycles specific to the respective wave shaping sub-circuit.
A method, comprising:
- providing scan data to each of a plurality of instances of an intellectual property core within an integrated circuit through scan data pipeline circuitry;
- providing one or more scan control signals to each of the plurality of instances through scan control signal pipeline circuitry;
- wherein the scan data pipeline circuitry and the scan control signal pipeline circuitry to each respective one of the plurality of instances are matched;
- and
- for each instance of the plurality of instances, selectively suppressing a scan clock to the instance for a number of clock cycles using a wave shaping circuit associated with the instance, wherein for each instance the selectively suppressing is based on detecting a trigger event on the one or more scan control signals provided to the instance.
Dependencies are inferred from the claim text.