Freedom from interference for aggregated communication channel handling using event-based processor extensions

A processor-based method for using time division multiplexing to interface a plurality of isolated execution contexts with a set of external communication channel hardware devices, comprising:

• storing, at an event latch, a plurality of n single-bit signals corresponding to a plurality of n hardware events generated by the set of external communication channel hardware devices, where each hardware event is stored at the event latch until an acknowledgment is received signaling that said hardware event has been processed;
• sequentially masking the plurality of n hardware events stored in the event latch with a sequence of n-bit event masks which are sequentially applied by a masking circuit in response to a plurality of timer interrupt signals generated by a timer circuit to generate, for each isolated execution context, a masked subset of hardware events specified by an n-bit event mask corresponding to said isolated execution context;
• and
• sequentially enabling, by a processor executing event-based programming code, each isolated execution context to communicate on the set of external communication channel hardware devices using only the masked subset of hardware events specified by the n-bit event mask corresponding to said isolated execution context to ensure freedom from interference between the plurality of isolated execution contexts when communicating with the set of external communication channel hardware devices.

A computer system, comprising:

• (a) a multithreaded processor executing event-based programming code to control communications between a plurality of isolated execution contexts and a set of external hardware devices;
• (b) an event register operatively connected to the multithreaded processor to store hardware events generated by the set of external hardware devices until an acknowledgment received from the multithreaded processor signals that the hardware event has been processed;
• (c) an event mask hardware operatively connected to the multithreaded processor to store a plurality of event masks, where each event mask is associated with a different isolated execution context running on the multithreaded processor;
• and
• (d) an event selection circuit operatively connected to the event register and event mask hardware to select, for each isolated execution context, a subset of the hardware events stored in the event register based on an event mask stored in the event mask hardware;
• wherein the multithreaded processor controls communications between the plurality of isolated execution contexts and the set of external hardware devices by allocating the hardware events stored in the event register to the plurality of isolated execution contexts based on the subset of the hardware events selected by the event selection circuit so that each isolated execution context is enabled to process only the subset of hardware events to ensure freedom from interference between the plurality of isolated execution contexts when communicating with the set of external hardware devices.