US 11,754,624 B1 · Programmable scan chain debug technique

Abstract

A method includes injecting scan patterns into an input of a decompressor that distributes the scan patterns to a plurality of scan chains whose outputs are coupled to inputs of a compressor, which provides a compressed scan test result representing the plurality of scan chains. The method also includes, in response to the compressed scan test result being indicative of failure, identifying a particular scan chain of the plurality of scan chains that is responsible for the failure by a debug circuit that is coupled to the input of the decompressor and to a compressor output. The debug circuit enables an output of any single scan chain of the plurality of scan chains to be available at the compressor output while suppressing outputs of all other scan chains of the plurality of scan chains.

Claims20

Dependent claims

A method comprising:

injecting scan patterns into an input of a decompressor that distributes the scan patterns to a plurality of scan chains whose outputs are coupled to inputs of a compressor, which provides a compressed scan test output representing the plurality of scan chains;
and
in response to the compressed scan test output being indicative of failure, identifying a particular scan chain of the plurality of scan chains that is responsible for the failure by a debug circuit that is coupled to the input of the decompressor and to a compressor output, and that enables an output of any single scan chain of the plurality of scan chains to be available at the compressor output while suppressing outputs of all other scan chains of the plurality of scan chains.

An integrated circuit comprising:

a scan compression circuit comprising:
a top-level input;
a top-level output;
a plurality of scan chains between the top-level input and the top-level output;
a decompressor between the top-level input and the plurality of scan chains, the decompressor configured to receive scan patterns via the top-level input and configured to distribute the scan patterns to the plurality of scan chains;
a compressor between the plurality of scan chains and the top-level output, the compressor configured to provide a compressed scan test output representing the plurality of scan chains;
and
a debug circuit coupled to the top-level input and to the top-level output, the debug circuit configured to enable an output of any single scan chain of the plurality of scan chains to be available at the top-level output while suppressing outputs of all other scan chains of the plurality of scan chains.

5 more elements

An apparatus comprising:

a debug circuit coupled to a top-level input and to a top-level output of a scan compression circuit comprising a plurality of scan chains, the debug circuit configured to enable an output of any single scan chain of the plurality of scan chains to be available at the top-level output while suppressing outputs of all other scan chains of the plurality of scan chains.

Dependencies are inferred from the claim text.

Programmable scan chain debug technique

Life of this patent

Programmable scan chain debug technique

Life of this patent

Abstract

Claims20