Throughput efficient Reed-Solomon forward error correction decoding

A non-transitory computer-readable medium comprising a stored description of a Reed-Solomon decoder circuit, which when compiled by a processor to generate a lower level description, which wen supplied to a fabrication system, causes the fabrication system to fabricate a Reed-Solomon decoder circuit comprising:

• a syndrome calculator circuit configured to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle;
• an error locator and error evaluator polynomial calculator circuit configured to compute error locator polynomials and error evaluator polynomials based on the syndrome values;
• an error location and error value calculator circuit configured to compute error locations based on the error locator polynomials and Forney numerator and denominator values based on the error evaluator polynomials;
• an error counter and error evaluator circuit configured to count errors based on the error locations and compute error magnitudes based on the Forney numerator and denominator values;
• and
• an error corrector circuit configured to correct errors in the first codeword and the second codeword based on the error counts and the error magnitudes.