A differential residue amplifier comprising:
- a differential input having a VIP input and a VIN input wherein VIP and VIN are complementary;
- a voltage shifter, receiving the differential input, for generating an upper differential input having a VIPN input and a VIPP input, and for generating a lower differential input having a VINP input and a VINN input, the voltage shifter shifting upward a common-mode voltage of the differential input to generate the upper differential input, the voltage shifter shifting downward the common-mode voltage of the differential input to generate the lower differential input;
- a true p-channel differential transistor having a gate receiving the VIPP input, and having a source connected to a power supply and a drain connected to a true upper node;
- a complement p-channel differential transistor having a gate receiving the VIPN input, and having a source connected to the power supply and a drain connected to a complement upper node;
- a true p-channel cascode transistor having a source connected to the true upper node, and a drain connected to a VON output;
- a complement p-channel cascode transistor having a source connected to the complement upper node, and a drain connected to a VOP output;
- a true n-channel differential transistor having a gate receiving the VINP input, and having a source connected to a ground and a drain connected to a true lower node;
- a complement n-channel differential transistor having a gate receiving the VINN input, and having a source connected to the ground and a drain connected to a complement lower node;
- a true n-channel cascode transistor having a source connected to the true lower node, and a drain connected to the VON output;
- a complement n-channel cascode transistor having a source connected to the complement lower node, and a drain connected to the VOP output;
- wherein the VOP output and the VON output form a differential output;
- wherein the voltage shifter comprises an AC-coupled input network that comprises:
- a true upper capacitor connected between the VIP input and the VIPP input;
- a true upper switch that closes to connect an upper shift voltage to the true upper capacitor during a zeroing phase of the differential residue amplifier;
- a complement upper capacitor connected between the VIN input and the VIPN input;
- a complement upper switch that closes to connect the upper shift voltage to the complement upper capacitor during the zeroing phase of the differential residue amplifier;
- a true lower capacitor connected between the VIP input and the VINP input;
- a true lower switch that closes to connect a lower shift voltage to the true lower capacitor during the zeroing phase of the differential residue amplifier;
- a complement lower capacitor connected between the VIN input and the VINN input;
- a complement lower switch that closes to connect the lower shift voltage to the complement lower capacitor during the zeroing phase of the differential residue amplifier;
- an input equalizing switch that closes to connect the VIP input to the VIN input during the zeroing phase of the differential residue amplifier;
- wherein the upper shift voltage is higher in voltage that the lower shift voltage;
- and
- a Switched-Capacitor Common-Mode Feedback (SCCMFB) circuit receiving an input bias voltage and receiving a common-mode voltage and generating an output bias voltage, the SCCMFB circuit comprising a ping circuit comprising:
- a first true capacitor connected between the VOP output and the output bias voltage;
- a first true staging capacitor;
- a first load switch that connects a first terminal of the first true staging capacitor with the common-mode voltage during the a phase;
- a second load switch that connects a second terminal of the first true staging capacitor with the input bias voltage during the first phase;
- a third load switch that connects the first terminal of the first true staging capacitor to the VOP output during a second phase;
- a fourth load switch that connects the second terminal of the first true staging capacitor to the output bias voltage during the second phase;
- a first complement capacitor connected between the VON output and the output bias voltage;
- a first complement staging capacitor;
- a fifth load switch that connects a first terminal of the first complement staging capacitor with the common-mode voltage during the first phase;
- a sixth load switch that connects a second terminal of the first complement staging capacitor with the input bias voltage during the first phase;
- a seventh load switch that connects the first terminal of the first complement staging capacitor to the VOP output during the second phase;
- an eighth load switch that connects the second terminal of the first complement staging capacitor to the output bias voltage during the second phase;
- a pong circuit that comprises the ping circuit wherein the first phase and the second phase are swapped;
- wherein a first instance of the SCCMFB circuit is an upper SCCMFB circuit that receives an upper bias voltage as the input bias voltage and generates the upper shift voltage as the output bias voltage;
- wherein a second instance of the SCCMFB circuit is a lower SCCMFB circuit that receives a lower bias voltage as the input bias voltage and generates the lower shift voltage as the output bias voltage;
- wherein the upper bias voltage is higher voltage that the lower bias voltage.