Decoupling FinFET capacitors

A method, the method comprising:

• providing a substrate having a first semiconductor fin and an adjacent second semiconductor fin with a shallow trench isolation (STI) feature between a bottom region of the first semiconductor fin and a bottom region of the second semiconductor fin;
• forming an electrical conductor over the STI feature and between the first semiconductor fin and the second semiconductor fin, wherein the electrical conductor is formed as part of a fin-type field effect transistor (FINFET) process, the FINFET process forming at least one of a metal layer or a gate layer;
• and
• depositing a dielectric layer between the first semiconductor fin and the second semiconductor fin and over the STI feature, wherein the depositing the dielectric layer includes forming a first spacer element extending from a sidewall of the first semiconductor fin to a first sidewall of the electrical conductor and a second spacer element extending from a sidewall of the second semiconductor fin to a second sidewall of the electrical conductor, the second sidewall of the electrical conductor opposing the first sidewall of the electrical conductor, wherein a top surface of the first spacer element is planar with a top surface of the first semiconductor fin wherein the first spacer element is formed directly on the sidewall of the first semiconductor fin.

A method, the method comprising:

• providing a substrate having a first semiconductor fin and an adjacent second semiconductor fin with a shallow trench isolation (STI) feature between a bottom region of the first semiconductor fin and a bottom region of the second semiconductor fin, wherein the first semiconductor fin and the adjacent second semiconductor fin have a length measured in a first direction from a top view and a width in a second direction from the top view, the length greater than the width;
• forming an electrical conductor over the STI feature and between the first semiconductor fin and the second semiconductor fin, wherein the electrical conductor is formed as part of a fin-type field effect transistor (FINFET) process, the FINFET process forming at least one of a metal layer or a gate layer, wherein the electrical conductor has a length measured in the first direction from the top view and a width in the second direction from the top view, wherein the length of the electrical conductor is greater than the width of the electrical conductor;
• and
• depositing a dielectric layer on an upper surface of the STI feature and between the first semiconductor fin and the second semiconductor fin and over the STI feature, wherein the depositing the dielectric layer includes forming a first spacer element abutting a sidewall of the first semiconductor fin and abutting a lower portion of a first sidewall of the electrical conductor, and forming a second spacer element abutting a sidewall of the second semiconductor fin and abutting a lower portion of a second sidewall of the electrical conductor, wherein an upper portion of the first sidewall of the electrical conductor and an upper portion of the second sidewall of the electrical conductor are free of the first spacer element and the second spacer element respectively, wherein each of the sidewall of the first semiconductor fin, the sidewall of the second semiconductor fin, the first sidewall of the electrical conductor, and the second sidewall of the electrical conductor extend in the first direction.