Multi-stage bit line pre-charge
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Cheng Wu, Kao-Cheng Lin, Chih-Cheng Yu, Pei-Yuan Li, Chien-Chen Lin, Wei Min Chan, Yen-Huei Chen
Life of this patent
Estimating the term…
Abstract
Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.
Claims20
A memory circuit, comprising:
- a bit cell responsive to a bit line signal line and a bit line bar signal line and configured to store a bit of data;
- and
- a pre-charge circuit configured to charge one of the bit line and bit line bar signal lines prior to a next read operation, wherein the pre-charge circuit comprises:
- a first pre-charge component;
- and
- a second pre-charge component;
- wherein:
- the first and second pre-charge components are individually controllable for charging the bit line and bit line bar signal lines;
- the first pre-charge component is configured to charge at a first average rate and the second pre-charge component is configured to charge, alone or in combination with the first pre-charge component, at a second average rate, the second average rate being faster than the first average rate;
- and
- the first pre-charge component comprises a first transistor having a first source/drain terminal connected to both the bit line signal line and the bit line bar signal line.
A method of controlling a multi-stage pre-charge circuit having a first pre-charge component and a second pre-charge component for charging one of a bit line signal line and a bit line bar signal line associated with a bit cell prior to a read operation, comprising:
- providing a first control signal to the first pre-charge component inhibiting charging during at least a portion of a read operation, wherein a word line associated with the bit cell is activated during the read operation;
- providing a second control signal to the second pre-charge component inhibiting charging during at least the portion of a read operation;
- transitioning the first control signal to enable charging by the first pre-charge component prior to deactivation of the word line;
- and
- transitioning the second control signal to enable charging by the second pre-charge component after transitioning the first control signal;
- wherein the first pre-charge component is configured to charge at a first average rate, the second pre-charge component is configured to charge, alone or in combination with the first pre-charge component, at a second average rate, the second average rate is faster than the first average rate, and the first pre-charge component comprises a transistor having a source/drain terminal connected to both the bit line signal line and the bit line bar signal line.
A memory comprising:
- a two-dimensional array of bit cells, each row of bit cells being associated with a data word, each column of bit cells being associated with a multi-stage pre-charge circuit;
- a plurality of multi-stage pre-charge circuits;
- and
- a pre-charge control circuit configured to provide a first control signal to first pre-charge components of the pre-charge circuits and a second control signal to second pre-charge components of the pre-charge circuits;
- wherein the first pre-charge components are configured to charge at a first average rate, the second pre-charge components are configured to charge, alone or in combination with the first pre-charge components, at a second average rate, the second average rate is faster than the first average rate, and each first pre-charge component comprises a transistor having a source/drain terminal connected to both a bit line signal line and a bit line bar signal line.
Dependencies are inferred from the claim text.