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US 11,742,810 B2Granted
Class AB buffer with multiple output stages
AssigneeTexas Instruments Incorporated
InventorsNitin Agarwal, Aniruddha Roy
Life of this patent
Estimating the term…
Abstract
A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.
Claims20
A buffer circuit comprising:
- an input stage that includes:
- a first cascode input;
- a second cascode input;
- a set of output nodes;
- a first transistor coupled between a first node and a second node, wherein the first transistor includes a gate coupled to the first cascode input;
- a first switch coupled between the second node and a first output node of the set of output nodes;
- a second switch coupled between the first output node and a third node;
- a third switch coupled between the second node and a second output node of the set of output nodes;
- a fourth switch coupled between the second output node and the third node;
- a second transistor coupled between the third node and a fourth node, wherein the second transistor includes a gate coupled to the second cascode input;
- a third transistor coupled between the first node and a fifth node, wherein the third transistor includes a gate coupled to the first cascode input;
- a fifth switch coupled between the fifth node and a third output node of the set of output nodes;
- a sixth switch coupled between the third output node and a sixth node;
- a seventh switch coupled between the fifth node and a fourth output node of the set of output nodes;
- an eighth switch coupled between the fourth output node and the sixth node;
- and
- a fourth transistor coupled between the sixth node and the fourth node;
- a first output stage that includes:
- a first output;
- a first cascode transistor coupled to the first output, wherein the first cascode transistor includes a gate coupled to the first output node of the input stage;
- and
- a second cascode transistor coupled to the first output, wherein the second cascode transistor includes a gate coupled to the fourth output node of the input stage;
- and
- a second output stage that includes:
- a second output;
- a third cascode transistor coupled to the second output, wherein the third cascode transistor includes a gate coupled to the second output node of the input stage;
- and
- a fourth cascode transistor coupled to the second output, wherein the fourth cascode transistor includes a gate coupled to the third output node of the input stage.
25 more elements
A buffer circuit comprising:
- an input stage that includes:
- a first output configured to provide a first signal based on a first switching signal;
- a first transistor coupled between a first node and a second node;
- a first switch coupled to the second node and the first output;
- a second switch coupled to the first output and a third node;
- a second transistor coupled between the third node and a fourth node;
- a second output configured to provide a second signal based on a second switching signal;
- a third switch coupled between the second node and the second output;
- a fourth switch coupled between the second output and the third node;
- a third output configured to provide a third signal based on the second switching signal;
- and
- a fourth output configured to provide a fourth signal based on the first switching signal;
- a first output stage that includes:
- a first buffer output;
- a first cascode transistor coupled to the first buffer output, wherein the first cascode transistor includes a gate coupled to the first output of the input stage;
- and
- a second cascode transistor coupled to the first buffer output, wherein the second cascode transistor includes a gate coupled to the fourth output of the input stage;
- and
- a second output stage that includes:
- a second buffer output;
- a third cascode transistor coupled to the second buffer output, wherein the third cascode transistor includes a gate coupled to the second output of the input stage;
- and
- a fourth cascode transistor coupled to the second buffer output, wherein the fourth cascode transistor includes a gate coupled to the third output of the input stage.
20 more elements
A buffer circuit comprising:
- an input stage comprising:
- a first cascode input;
- a second cascode input;
- a set of output nodes;
- a first transistor coupled between a first node and a second node, wherein the first transistor includes a gate coupled to the first cascode input;
- a first switch coupled between the second node and a first output node of the set of output nodes;
- a second switch coupled between the first output node and a third node;
- a third switch coupled between the second node and a second output node of the set of output nodes;
- a fourth switch coupled between the second output node and the third node;
- a second transistor coupled between the third node and a fourth node, wherein the second transistor includes a gate coupled to the second cascode input;
- a third transistor coupled between the first node and a fifth node, wherein the third transistor includes a gate coupled to receive a feedback signal;
- a fifth switch coupled between the fifth node and a third output node of the set of output nodes;
- a sixth switch coupled between the third output node and a sixth node;
- a seventh switch coupled between the fifth node and a fourth output node of the set of output nodes;
- an eighth switch coupled between the fourth output node and the sixth node;
- and
- a fourth transistor coupled between the sixth node and the fourth node, wherein the fourth transistor includes a gate coupled to the second cascode input;
- a first output stage that includes:
- a first output;
- a first cascode transistor coupled to the first output, wherein the first cascode transistor includes a gate coupled to the first output node of the input stage;
- and
- a second cascode transistor coupled to the first output, wherein the second cascode transistor includes a gate coupled to the fourth output node of the input stage;
- and
- a second output stage that includes:
- a second output;
- a third cascode transistor coupled to the second output, wherein the third cascode transistor includes a gate coupled to the second output node of the input stage;
- and
- a fourth cascode transistor coupled to the second output, wherein the fourth cascode transistor includes a gate coupled to the third output node of the input stage.
25 more elements
Dependencies are inferred from the claim text.