Systems and methods for defining a dependency of preceding and succeeding instructions
AssigneeArm Limited
InventorsWei Wang, Thomas Edward Shull
Life of this patent
Estimating the term…
Abstract
In a particular implementation, a method includes: receiving, at a computing device, first and second instructions of a plurality of instructions obtained from a memory, where the first instruction corresponds to a preceding instruction of a second instruction, and where the second instruction corresponds to a succeeding instruction of the first instruction; determining a dependency of the first and second instructions; sending the first and second instructions to an issue queue of the computing device; executing, at the computing device, the first and second instructions; and completing, at the computing device, the first and second instructions.
Claims20
A method comprising:
- identifying a first instruction of a plurality of instructions as a preceding instruction;
- identifying a second instruction of the plurality of instructions as a succeeding instruction;
- defining a dependency based on the identified first and second instructions, wherein the dependency corresponds to a predetermined ordered constraint
- generating, at a computing device, complementary parameters indicating the dependency of the first and second instructions,
- selecting a stage of dependency enforcement based on an instruction-type of the first and second instructions, wherein stages of dependency enforcement comprise at least one of an issue queue or a writeback buffer, and
- executing, at the issue queue or the writeback buffer of the computing device, the dependency enforcement of the first and second instructions based on the instruction-type.
A method comprising:
- receiving, at a computing device, first and second instructions of a plurality of instructions obtained from a memory, wherein the first instruction corresponds to a preceding instruction of a second instruction, and wherein the second instruction corresponds to a succeeding instruction of the first instruction;
- determining a dependency of the first and second instructions;
- determining an instruction-type of the first and second instructions;
- selecting a stage of dependency enforcement based on the instruction-type, wherein stages of dependency enforcement comprise at least one of an issue queue or a writeback buffer;
- sending the first and second instructions to the issue queue of the computing device;
- executing, at the issue queue or the writeback buffer of the computing device, the dependency enforcement of the first and second instructions based on the instruction-type;
- and
- completing, at the computing device, the first and second instructions.
An apparatus comprising:
- a non-transitory computer-readable storage medium;
- at least one processor;
- and
- program code stored on the computer-readable storage medium and configured upon
- execution by the at least one processor to:
- receive, at a computing device, first and second instructions of a plurality of instructions obtained from a memory, wherein the first instruction corresponds to a preceding instruction of the second instruction, and wherein the second instruction corresponds to a succeeding instruction of the first instruction;
- determine a dependency of the first and second instructions;
- determine an instruction-type of the first and second instructions;
- select a stage of dependency enforcement based on the instruction-type, wherein stages of dependency enforcement comprise at least one of an issue queue or a writeback buffer;
- send the first and second instructions to the issue queue of the computing device;
- execute, at the issue queue or the writeback buffer of the computing device, the dependency enforcement of the first and second instructions;
- and
- complete, at the computing device, the first and second instructions.
Dependencies are inferred from the claim text.