Semiconductor memory device having an electrically floating body transistor

An integrated circuit comprising:

• an array of memory cells formed in a semiconductor, the array comprising:
• a plurality of semiconductor memory cells arranged in a matrix of rows and columns wherein the rows of memory cells define a first direction and the columns of memory cells define a second direction, and each of said memory cells comprising:
• a floating body region defining at least a portion of a surface of the semiconductor memory cell;
• a first region located at a surface of said floating body region;
• and
• a second region located below said floating body region, said second region being commonly connected to at least two of said semiconductor memory cells in said matrix;
• wherein said array further comprises gate regions, each said gate region overlaying two of said semiconductor memory cells along the second direction;
• wherein a state of said semiconductor memory cell, which may be a first state or a second state, is stored in said floating body region;
• wherein said second region is configured to generate impact ionization when the semiconductor memory cell is in one of said first and second states, and wherein said second region is configured so as not to generate impact ionization when the semiconductor memory cell is in the other of said first and second states;
• a third region having a conductivity type the same as a conductivity type of said second region, said third region being electrically connected to said second region;
• and
• a first control circuitry configured to provide electrical signals to said second regions.