Phase interpolator circuitry for a bit-level mode retimer

Phase interpolator circuitry, comprising:

• a first phase interpolator configured to:
• receive a phase control signal from a clock and data recovery circuit,
• generate, based on the phase control signal, an output clock signal, and
• provide the output clock signal to an analog-to-digital converter;
• a second phase interpolator configured to:
• receive the phase control signal,
• generate, based on the phase control signal, a further output clock signal, and
• provide the further output clock signal to a transmitter to track a plurality of data packets;
• and
• a digital filter coupled between the first phase interpolator and the second phase interpolator, and coupled between the clock data recovery circuit and the second phase interpolator, the digital filter configured to perform digital filtering of the phase control signal to the second phase interpolator to remove or reduce one or more frequency components associated with jitter noise.