Memory package, semiconductor device, and storage device

A semiconductor device comprising:

• a first receiver configured to output a data signal based on a first input signal received from outside the semiconductor device;
• a second receiver configured to output a raw clock signal based on a second input signal received from outside the semiconductor device;
• a delay locked loop circuit configured to output a first delay code;
• a first sampler configured to sample the data signal in synchronization with a clock signal;
• a counter circuit configured to output a second delay code generated based on a signal detected in at least one of an input terminal and an output terminal of the first sampler;
• and
• a delay cell configured to output a delay clock signal generated by delaying the raw clock signal by applying delays determined based on the first delay code and the second delay code, and output the clock signal generated by removing a delay according to the first delay code from the delay clock signal when a phase difference between the data signal and the delay clock signal corresponds to one unit interval of the data signal.

A storage device comprising:

• a controller configured to sequentially execute a plurality of training operations;
• a memory chip configured to output a first signal and a second signal having the same phase through a first pad and a second pad, respectively, while at least one of the training operations is executed;
• and
• an interface chip connected between the controller and the memory chip, and the interface chip including:
• a first receiver configured to output a data signal based on the first signal;
• a second receiver configured to output a raw clock signal based on the second signal;
• a first sampler configured to sample the data signal in synchronization with a clock signal;
• and
• a delay circuit configured to:
• output a delay clock signal by applying a first delay code corresponding to a first delay determined regardless of a phase difference between the data signal and the delay clock signal detected at a respective input terminal of the first sampler and applying a second delay code corresponding to a second delay determined based on the phase difference between the data signal and the delay clock signal detected at the respective input terminal of the first sampler, and
• output the clock signal by removing the first delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.