Clock signal delay path unit and semiconductor memory device including the same

A semiconductor memory device, comprising:

• a clock signal input buffer configured to buffer an external clock signal applied from the outside, and to output a buffered clock signal;
• a delay lock loop configured to receive the buffered clock signal, and to generate a delayed clock signal that is delay-locked to the external clock signal;
• a clock signal delay path unit configured to delay and invert the delayed clock signal to generate n internal clock signals, a data strobe signal, and an inverted data strobe signal;
• a memory cell array including a plurality of memory cells, and outputting data stored in memory cells selected in response to a plurality of word line selection signals and a plurality of column selection signals;
• a data read path unit configured to receive the data, and to convert the data into serial data to generate n pieces of data;
• a data output unit configured to drive the n pieces of data in response to the n internal clock signals;
• and
• a data strobe signal output unit configured to drive the output data strobe signal and the inverted output data strobe signal, wherein:
• the clock signal delay path unit includes n+2 branch delay units each including:
• at least one first delay cell including a first root signal line for delaying and transmitting the delayed clock signal, a first repeater configured to transmit the delayed clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the delayed clock output from the first repeater;
• a second delay cell including a first inverting circuit configured to invert the delayed clock signal provided from the first delay cell to generate an inverted delayed clock signal;
• and
• at least one third delay cell including a first branch signal line for delaying and transmitting the inverted delayed clock signal provided from the second delay cell, a second repeater configured to transmit the inverted delayed clock signal transmitted through the first branch signal line without signal attenuation, and a second branch signal line for delaying and transmitting the inverted delay clock signal output from the second repeater,
• wherein each of the first root signal line, the second root signal line, the first branch signal line, and the second branch signal line is a long metal line, and
• the n+2 branch delay units generate the n internal clock signals, the output data strobe signal, and the inverted output data strobe signal.

A semiconductor memory device, comprising:

• a read enable signal input buffer configured to buffer a read enable signal applied from the outside, and to output a buffered read enable signal;
• an inverted read enable signal input buffer configured to buffer an inverted read enable signal applied from the outside, and to output a buffered inverted read enable signal;
• a read enable signal delay path configured to delay and invert the buffered read enable signal and the buffered inverted read enable signal to generate n internal clock signals, an output data strobe signal, and an inverted output data strobe signal;
• a memory cell array including a plurality of memory cells and outputting data stored in memory cells selected in response to a plurality of word line selection signals, a plurality of source line selection signals, a plurality of ground selection signals, and a plurality of column selection signals;
• a page buffer configured to buffer the data to generate read data;
• a data read path unit configured to receive the read data, and to convert the data into serial data to generate n pieces of data;
• a data output unit configured to drive the n pieces of data in response to the n internal clock signals;
• and
• a data strobe signal output unit configured to drive the output data strobe signal and the inverted output data strobe signal, wherein:
• the read enable signal delay path includes n+2 branch delay units each including:
• at least one first delay cell including a first root signal line pair for delaying and transmitting a read enable signal pair including the buffered read enable signal and the buffered inverted read enable signal, a first repeater configured to transmit the read enable signal pair transmitted through the first root signal line pair without signal attenuation, and a second root signal line pair for delaying and transmitting the read enable signal pair output from the first repeater;
• a second delay cell including a first inverting circuit configured to invert the read enable signal pair provided from the first delay cell, and to output an inverted read enable signal pair;
• and
• at least one third delay cell including a first branch signal line pair for delaying and transmitting the inverted read enable signal pair provided from the second delay cell, a second repeater configured to transmit the inverted read enable signal pair transmitted through the first branch signal line pair without signal attenuation, and a second branch signal line pair for delaying and transmitting the inverted read enable signal pair output from the second repeater,
• wherein each of the first root signal line pair, the second root signal line pair, the first branch signal line pair, and the second branch signal line pair is a long metal line pair, and
• the n+2 branch delay units generate the n internal clock signals, the output data strobe signal, and the inverted output data strobe signal.