Integrated circuit devices with well regions and methods for forming the same

A method comprising:

• forming a deep well region of a first conductivity type in a substrate, wherein the deep well region extends to a top-most surface of the substrate;
• implanting a portion of the deep well region to form a bottom gate;
• implanting the deep well region to form a well ring extending from a top surface of the substrate to the bottom gate, wherein the well ring and the bottom gate are of a second conductivity type opposite the first conductivity type, and wherein the well ring encircles the bottom gate;
• implanting a portion of the deep well region overlying and contacting the bottom gate to form a channel region of the first conductivity type;
• implanting a portion of the deep well region overlying the channel region to form a first top gate and a second top gate of the second conductivity type, wherein an interface between the channel region and the first top gate is substantially coplanar with a bottom surface of an isolation region extending from a top surface of the substrate into the substrate, and the isolation region has an edge contacting the first top gate;
• and
• performing a first source/drain implantation to form a first source region and a second source region on opposite sides of the first top gate and the second top gate and a first drain region between the first top gate and the second top gate, wherein the first source region, the second source region, and the first drain region are of the first conductivity type, and wherein the first source region, the second source region, and the first drain region overlap the channel region and the bottom gate, and wherein a first shortest distance between the first drain region and the first top gate is substantially different from a second shortest distance between the first source region and the first top gate.

A method comprising:

• forming a deep well region of a first conductivity type in a semiconductor substrate by implanting impurities into the semiconductor substrate, wherein the deep well region extends to a top-most surface of the semiconductor substrate;
• forming Shallow Trench Isolation (STI) regions in the semiconductor substrate;
• forming a channel region in the semiconductor substrate, wherein the channel region is of a first conductivity type;
• implanting the deep well region to form a well region, wherein the well region is of a second conductivity type opposite the first conductivity type and wherein the well region forms a well ring in a plan view;
• implanting the deep well region to form a pickup region overlying and contacting the well region, wherein the pickup region is of the second conductivity type and wherein the pickup region forms a pickup ring in a plan view;
• implanting the deep well region to form a first gate overlying and contacting the channel region, wherein the first gate extends to the top-most surface of the semiconductor substrate and wherein an entirety of the first gate is spaced apart from the pickup ring in the plan view;
• forming a Metal-Oxide-Semiconductor (MOS) device, wherein source/drain regions of the MOS device are implanted while implanting the deep well region to form the first gate;
• implanting the deep well region to form a second gate underlying and contacting the channel region, wherein the first gate and the second gate are of a second conductivity type opposite the first conductivity type, and wherein the well ring encircles the second gate;
• and
• implanting the deep well region to form a first source/drain region and a second source/drain region over and contacting the channel region, wherein the first and the second source/drain regions are on opposite sides of the first gate, and are of the first conductivity type.