Programmable memory cell, memory array and reading and writing method thereof

A programmable storage array, comprising:

• a plurality of anti-fuse groups;
• a plurality of output terminals, wherein each of the plurality of anti-fuse groups connects to one of the plurality of output terminals in a one-to-one correspondence, wherein each of the plurality of anti-fuse groups comprises a first anti-fuse and a second anti-fuse, wherein the first anti-fuse is connected between a first power terminal and a corresponding one of the plurality of output terminals, and the second anti-fuse is connected between a second power terminal and a corresponding one of the plurality of output terminals;
• a plurality of third switch units;
• and
• a plurality of position signal terminals, wherein the plurality of third switch units and the plurality of output terminals are arranged in a one-to-one correspondence, wherein each of the plurality of third switch units connects to one of the plurality of position signal terminals in a one-to-one correspondence, wherein the plurality of third switch units is connected to a third power terminal;
• and
• wherein each of the plurality of third switch units responds to a signal of a corresponding one of the plurality of position signal terminals to connect the third power terminal and the corresponding one of the plurality of output terminals.

A method for reading and writing a programmable storage array, comprising a reading phase and a writing phase:

• wherein in the writing phase:
• in a first stage, inputting a first high-voltage level signal to a first power terminal, inputting a low-voltage level signal to a second power terminal and a third power terminal, and inputting an effective-voltage level signal to a preset position signal terminal to turn on a third switch unit, in order to breakdown a corresponding first anti-fuse;
• in a second stage, inputting the first high-voltage level signal to the second power terminal, inputting the low-voltage level signal to the first power terminal and the third power terminal, and inputting the effective-voltage level signal to the preset position signal terminal to turn on the third switch unit, in order to breakdown a corresponding second anti-fuse;
• and
• wherein in the reading phase:
• inputting a second high-voltage level signal to the first power terminal, inputting a low-voltage level signal to the second power terminal and the third power terminal, and inputting an invalid-voltage level signal to the position signal terminal to turn off the third switch unit.