Phase locking multiple clocks of different frequencies
AssigneeSeagate Technology LLC
InventorsZheng Wu, Jason Bellorado
Life of this patent
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Abstract
Systems and methods are disclosed for phase locking of a clock. In some embodiments, a phase locked clock (PLC) module can phase-lock a write clock to a media written with multiple servo zones of different frequencies. In some implementations, this can be utilized to perform a self-servo write (SSW) of a disc surface within a hard disc drive (HDD). A PLC module can perform a method of writing with a single frequency phase coherently while a read element passes over servo zones with different frequencies. While the PLC module can perform such methods for a SSW process, the methods can also be utilized for other applications that can benefit from writing with a single frequency phase coherently based on servo zones with different frequencies.
Claims20
An apparatus comprising:
- a data channel including a phase lock clock (PLC) module configured to:
- synchronize multiple servo clocks to a reference clock, the multiple servo clocks used to read servo data from servo zones with different frequencies, and the reference clock used to perform a write of a spiral pattern utilizing a single frequency phase;
- and
- after synchronization of the multiple servo clocks, perform the write to a first data storage medium while a write head is positioned based on the servo zones with different frequencies.
A phase-locking circuit comprising:
- a write clock circuit configured to produce a write clock;
- a first servo channel circuit;
- a second servo channel circuit;
- a first servo clock circuit configured to produce a first read clock aligned to a first frequency and configured to be utilized by the first servo channel circuit to demodulate a first servo zone having the first frequency and generate first servo timing marks;
- a second servo clock circuit configured to produce a second read clock aligned to a second frequency and configured to be utilized by the second servo channel circuit to demodulate a second servo zone having the second frequency and generate second servo timing marks;
- a disc locked clock (DLC) control circuit configured to maintain phase coherency based on the first servo timing marks and the second servo timing marks when switching from the first servo zone to the second servo zone;
- the phase-locking circuit configured to:
- synchronize the first servo clock and the second servo clock to the write clock;
- and
- after synchronization of the first and second servo clocks, perform a write to a first data storage medium utilizing a single frequency phase while a write head is positioned based on both the first servo zone and the second servo zone.
A memory device storing instructions that when executed cause a processing circuit to perform a method comprising:
- synchronizing, in a data channel, multiple servo read clocks to a reference clock;
- and
- after synchronization of the multiple servo read clocks, applying the reference clock to perform a write of a spiral pattern to a first data storage medium utilizing a single frequency phase while a write head is positioned based on servo zones with different frequencies.
Dependencies are inferred from the claim text.