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US 11,734,608 B2Granted
Address interleaving for machine learning
AssigneeMarvell Asia Pte Ltd
InventorsAvinash Sodani, Ramacharan Sundararaman
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Abstract
A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.
Claims16
A system to support an operation, comprising:
- an inference engine comprising one or more processing tiles, wherein each processing tile comprises at least one or more of
- an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile;
- and
- one or more processing units configured to perform one or more computation tasks of the operation on data in the OCM by executing a set of task instructions;
- and
- a data streaming engine configured to stream data between the a memory and the OCMs of the one or more processing tiles of the inference engine, wherein the data streaming engine is configured to interleave an address associated with a memory access transaction for accessing the memory, wherein a subset of bits of the interleaved address is used to determine an appropriate communication channel through which to access the memory;
- and
- a network interface controller configured to support address interleaving for a burst length greater than a burst length of the address.
5 more elements
A system comprising:
- an inference engine configured to receive the data and to perform one or more computation tasks operation associated with the data;
- a master configured to:
- interleave an address associated with a memory access transaction for accessing a memory, and wherein the master is further configured to stream a content associated with the accessing to the inference engine,
- move one or more communication channel identifier bits within the address to the highest order address bits, wherein the communication channel identifier bits identify an appropriate communication channel through which to access the memory, and
- shift down the address bits with a bit order higher than a bit order of the communication channel identifier bits before the moving, wherein the shifting down is by a same order as a number of the communication channel identifier bits, and wherein the moving and the shifting down forms the interleaved address;
- and
- a network interface controller configured to support address interleaving for a burst length greater than a burst length of the address.
4 more elements
A method, comprising:
- interleaving an address associated with a memory access transaction for accessing a memory, wherein interleaving of the address is for a burst length greater than a burst length of the address;
- utilizing a subset of bits of the interleaved address to determine an appropriate communication channel through which to access the memory;
- streaming data associated with the memory accessing transaction from the memory to an inference engine;
- and
- performing one or more computation tasks operation associated with the data via the inference engine.
2 more elements
Dependencies are inferred from the claim text.