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US 11,733,972 B2Granted
Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address
AssigneeVentana Micro Systems Inc.
InventorsJohn G. Favor, Srivatsan Srinivasan
Life of this patent
Estimating the term…
Abstract
A microprocessor that mitigates side channel attacks. The microprocessor includes a data cache memory and a load unit that receive a load operation that specifies a load address. The processor performs speculative execution of instructions and executes instructions out of program order. The load unit detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist and provides random load data as a result of the execution of the load operation.
Claims33
A microprocessor for mitigating side channel attacks,
- comprising:
- a load unit that receives a series of load operations, each of which specifies a load address;
- and
- a data cache memory;
- wherein the microprocessor performs speculative execution of instructions;
- wherein the microprocessor executes instructions out of program order;
- and
- wherein the load unit, for each load operation of a plurality of load operations of the series of load operations:
- detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist;
- and
- provides random load data as a result of the execution of the load operation;
- wherein the load unit provides new random load data for each different load operation of the plurality of load operations;
- and
- wherein the load unit provides the random load data without accessing system memory even when the load address misses in the data cache memory.
11 more elements
A method for mitigating side channel attacks, comprising:
- in a microprocessor that performs speculative execution of instructions and executes instructions out of program order:
- issuing a series of load operations to a load unit of the microprocessor for execution, wherein each of the load operations specifies a load address;
- for each load operation of a plurality of load operations of the series of load operations:
- detecting, by the load unit, that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist;
- and
- providing, by the load unit, random load data as a result of the execution of the load operation;
- wherein the load unit provides new random load data for each different load operation of the plurality of load operations;
- wherein the microprocessor further comprises a data cache memory;
- and
- wherein the load unit provides the random load data without accessing system memory even when the load address misses in the data cache memory.
7 more elements
A non-transitory computer-readable medium having
- instructions stored thereon that are capable of causing or configuring a microprocessor for mitigating side channel attacks, wherein the microprocessor speculatively executes instructions out of program order, wherein the microprocessor is configured by the instructions to perform operations comprising:
- issuing a series of load operations to a load unit of the microprocessor for execution, wherein each of the load operations specifies a load address;
- and
- for each load operation of a plurality of load operations of the series of load operations:
- detecting, by the load unit, that the load operation does not have permission to access the load address;
- and
- providing, by the load unit, random load data as a result of the execution of the load operation;
- wherein the load unit provides new random load data for each different load operation of the plurality of load operations
- wherein the microprocessor further comprises a data cache memory;
- and
- wherein the load unit provides the random load data without accessing system memory even when the load address misses in the data cache memory.
8 more elements
A microprocessor for mitigating side channel attacks, comprising:
- a load unit that receives a series of load operations, each of which specifies a load address;
- and
- a store unit that receives a store operation that specifies a store address;
- wherein the microprocessor performs speculative execution of instructions;
- wherein the processor executes instructions out of program order;
- and
- wherein the load unit, for each load operation of a plurality of load operations of the series of load operations:
- detects that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist;
- and
- provides random load data as a result of the execution of the load operation;
- wherein the load unit provides new random load data for each different load operation of the plurality of load operations;
- and
- wherein the store unit:
- detects that the store operation does not have permission to access the store address or that the store address specifies a location for which a valid address translation does not currently exist;
- and
- provides random store data to a store queue as a result of the execution of the store operation.
13 more elements
A method for mitigating side channel attacks, comprising:
- in a microprocessor that performs speculative execution of instructions and executes instructions out of program order:
- issuing a series of load operations to a load unit of the microprocessor for execution, wherein each of the load operations specifies a load address;
- for each load operation of a plurality of load operations of the series of load operations:
- detecting, by the load unit, that the load operation does not have permission to access the load address or that the load address specifies a location for which a valid address translation does not currently exist;
- and
- providing, by the load unit, random load data as a result of the execution of the load operation;
- wherein the load unit provides new random load data for each different load operation of the plurality of load operations;
- issuing a store operation to a store unit of the microprocessor for execution, wherein the store operation specifies a store address;
- detecting, by the store unit, that the store operation does not have permission to access the store address or that the store address specifies a location for which a valid address translation does not currently exist;
- and
- providing, by the store unit, random store data to a store queue as a result of the execution of the store operation.
8 more elements
Dependencies are inferred from the claim text.