De-skew circuit, de-skew method, and receiver

A de-skew method used with a de-skew circuit comprising N data synchronization circuits and a controller, wherein the de-skew method comprises steps of:

• the N data synchronization circuits respectively receiving N input data streams with timing skew from a physical layer;
• an nth data synchronization circuit among the N data synchronization circuits changing a voltage of an nth command detection signal and storing an nth input data stream among the N input data streams when the nth input data stream satisfies a single lane condition;
• the controller receiving the nth command detection signal from the nth data synchronization circuit;
• the N data synchronization circuits outputting the stored N input data streams as N timing-aligned data streams with aligned timing in response to a pop signal changed by the controller when a global lane condition is satisfied, wherein the global lane condition is related to the single lane condition;
• and
• the de-skew circuit transmitting the N timing-aligned data streams to a media access control wherein n and N are positive integers and n is less than or equal to N.

A receiver, comprising:

• a physical layer, configured to generate N input data streams with timing skew;
• a media access control, configured to receive N timing-aligned data streams with aligned timing;
• and
• a de-skew circuit, electrically connected to the physical layer and the media access control, comprising:
• N data synchronization circuits, configured to transform the N input data streams into the N timing-aligned data streams, wherein an nth data synchronization circuit among the N data synchronization circuits comprises:
• an nth command detector, configured to change a voltage of an nth command detection signal when an nth input data stream among the N input data streams satisfies a single lane condition;
• and
• an nth buffer, configured to store the nth input data stream in response to a voltage change of the nth command detection signal;
• and
• a controller, electrically connected to the N data synchronization circuits, configured to receive the nth command detection signal and change a voltage of a pop signal connected to the nth buffer when a global lane condition is satisfied, wherein the nth buffer outputs the stored nth input data stream as an nth timing-aligned data stream of the N timing-aligned data streams in response to a voltage change of the pop signal, wherein n and N are positive integers and n is less than or equal to N.