Method and apparatus for low latency charge coupled decision feedback equalization

A mixed signal receiver, comprising:

• a first sample and hold circuit having a first S/H input terminal to receive an analog input signal and a first S/H output terminal directly coupled to a first common node, wherein the first sample and hold circuit is configured to perform cycles at a symbol rate with each cycle including a sample phase and a hold phase, and wherein the first sample and hold circuit is configured to track the analog input signal on the first S/H output terminal during the sample phase and to generate a high impedance on the first S/H output terminal during the hold phase to enable a sampled analog output voltage to be modulated during the hold phase;
• a first data slicer having a first slicer input terminal coupled to the first common node such that the first data slicer is directly driven by the first S/H output terminal;
• and
• a first data-driven charge coupling digital-to-analog converter (DAC) including
• (i) a DAC input terminal to receive a first digital signal from a first digital output of the first data slicer,
• (ii) a DAC output terminal directly coupled to the first common node,
• (iii) a plurality of capacitor modules configured to be pre-charged such that the DAC output terminal tracks an output voltage on the first S/H output terminal during the sample phase, and
• (iv) logic components at an interface of the first data-driven charge coupling DAC to receive the first digital signal and to control voltages applied to the plurality of capacitor modules based on the first digital signal such that if the logic components toggle a voltage on the plurality of capacitor modules then charge is capacitively coupled to or from the first common node during an immediately subsequent hold phase so that the capacitively coupled charge modulates the output voltage at the first S/H output terminal during the hold phase.