Circuit apparatus and oscillator
AssigneeSeiko Epson Corporation
InventorsKohei Beppu, Takehiro Yamamoto
Life of this patent
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Abstract
A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.
Claims9
A circuit apparatus comprising:
- an oscillation circuit that generates an oscillation signal;
- a first buffer circuit that outputs a first clock signal based on the oscillation signal;
- a second buffer circuit that outputs a second clock signal based on the first clock signal;
- a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal;
- a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal;
- and
- a switch circuit that electrically couples or decouples the first node to or from the first terminal;
- and
- a resistive element electrically coupled to and disposed between the first node and the switch circuit,
- wherein a rise period of the first clock signal is shorter than a rise period of the second clock signal.
A circuit apparatus comprising:
- an oscillation circuit that generates an oscillation signal;
- a first buffer circuit that outputs a first clock signal based on the oscillation signal;
- a second buffer circuit that outputs a second clock signal based on the first clock signal;
- a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal;
- a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal;
- a switch circuit that electrically couples or decouples the first node to or from the first terminal;
- and
- an RC filter eclectically coupled to and disposed between the first node and the switch circuit,
- wherein a rise period of the first clock signal is shorter than a rise period of the second clock signal.
Dependencies are inferred from the claim text.