Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
AssigneeZeno Semiconductor, Inc.
InventorYuniarto Widjaja
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Abstract
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
Claims20
A semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
- a substrate;
- a transistor comprising a source region, a first floating body region, a drain region, and a gate;
- a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region, wherein:
- one of said cathode region and said anode region comprises said substrate,
- a state of said memory cell is stored in said first floating body region,
- said first floating body region and said second floating body region are common,
- said silicon controlled rectifier device maintains a state of said memory cell, and
- said transistor is usable to access said memory cell;
- and
- a nonvolatile memory comprising a resistance change element configured to store data stored in said first floating body region upon transfer to said nonvolatile memory;
- wherein said buried layer region is commonly connected to at least two of said memory cells.
An integrated circuit comprising:
- a semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
- a substrate;
- a transistor comprising a source region, a first floating body region, a drain region, and a gate;
- a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region, wherein:
- one of said cathode region and said anode region comprises said substrate,
- a state of said memory cell is stored in said first floating body region, said first floating body region and said second floating body region are common,
- said silicon controlled rectifier device maintains a state of said memory cell, and
- said transistor is usable to access said memory cell;
- a nonvolatile memory comprising a resistance change element configured to store data stored in said first floating body region upon transfer to said nonvolatile memory;
- wherein said buried layer region is commonly connected to at least two of said memory cells;
- and
- a control circuit configured to perform transfer of said data stored in said first floating body region to said nonvolatile memory.
Dependencies are inferred from the claim text.