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US 11,721,646 B2Granted
Integrated ultralong time constant time measurement device and fabrication process
AssigneeSTMicroelectronics (Rousset) SAS
InventorsAbderrezak Marzaki, Pascal Fornara
Life of this patent
Estimating the term…
Abstract
An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.
Claims29
An integrated circuit, comprising:
- a semiconductor substrate having a front face;
- a first trench and second trench extending into the semiconductor substrate from the front face;
- a first conductive region housed in each of the first trench and second trench and insulated from the semiconductor substrate by an insulating liner;
- a dielectric layer extending over the front face of the semiconductor substrate and further extending at least partially over the first conductive region in the first trench and at least partially over the first conductive region in the second trench;
- wherein the dielectric layer has a thickness allowing charge to flow by direct tunneling effect;
- a second conductive region on the dielectric layer;
- wherein the first conductive region in the first trench, the dielectric layer and the second conductive region form a first capacitor;
- wherein the first conductive region in the second trench, the dielectric layer and the second conductive region form a second capacitor connected in series with the first capacitor;
- a semiconductor well that is housed in the semiconductor substrate;
- a first contact and a second contact which are electrically connected by an electrical path through the semiconductor well, wherein said electrical path comprises a section of said semiconductor well that is located underneath a bottom of the first and second trenches;
- and
- a detection circuit configured to detect an electrical discontinuity in the semiconductor well between the first contact and the second contact.
9 more elements
An integrated circuit, comprising:
- a semiconductor substrate having a front face;
- a first trench and second trench extending into the semiconductor substrate from the front face;
- a first conductive region housed in each of the first trench and second trench and insulated from the semiconductor substrate by an insulating liner;
- a dielectric layer extending over the front face of the semiconductor substrate and further extending at least partially over the first conductive region in the first trench and at least partially over the first conductive region in the second trench;
- wherein the dielectric layer has a thickness allowing charge to flow by direct tunneling effect;
- a second conductive region on the dielectric layer;
- wherein the first conductive region in the first trench, the dielectric layer and the second conductive region form a first capacitor;
- wherein the first conductive region in the second trench, the dielectric layer and the second conductive region form a second capacitor connected in series with the first capacitor;
- and
- a capacitive storage element that is electrically coupled to the first conductive region of one the first and second capacitors;
- wherein the first and second capacitors in series are configured to discharge the capacitive storage element and to generate at the second conductive region a signal that is representative of both the discharging of the capacitive storage element and a duration that has elapsed from a start of an operation of discharging the capacitive storage element.
8 more elements
An integrated circuit, comprising:
- a semiconductor substrate having a front face;
- a trench extending into the semiconductor substrate from the front face;
- a first conductive region housed in the trench and insulated from the semiconductor substrate by an insulating liner;
- a dielectric layer extending over the front face of the semiconductor substrate and further extending at least partially over the first conductive region in the trench;
- wherein the dielectric layer has a thickness allowing charge to flow by direct tunneling effect;
- a second conductive region on the dielectric layer;
- wherein the first conductive region in the trench, the dielectric layer and the second conductive region form a capacitor;
- a capacitive storage element that is electrically coupled to the first conductive region of the capacitor;
- and
- wherein the capacitor is configured to discharge the capacitive storage element and to generate a signal that is representative of both the discharging of the capacitive storage element and a discharge duration.
7 more elements
An integrated circuit, comprising:
- a semiconductor substrate having a front face;
- a first trench and second trench extending into the semiconductor substrate from the front face;
- a first conductive region housed in each of the first trench and second trench and insulated from the semiconductor substrate by an insulating liner;
- a dielectric layer extending over the front face of the semiconductor substrate and further extending at least partially over the first conductive region in the first trench and at least partially over the first conductive region in the second trench;
- wherein the dielectric layer has a thickness allowing charge to flow by direct tunneling effect;
- a second conductive region on the dielectric layer;
- wherein the first conductive region in the first trench, the dielectric layer and the second conductive region form a first capacitor;
- and
- wherein the first conductive region in the second trench, the dielectric layer and the second conductive region form a second capacitor connected in series with the first capacitor;
- a first comparator having an input coupled to the second conductive region, said first comparator configured to compare a physical quantity at said second conductive region to a first threshold;
- a second comparator having an input coupled to first conductive region of one of the first and second capacitors, said second comparator configured to compare a physical quantity at said first conductive region to a second threshold;
- a capacitive storage element that is electrically coupled to the first conductive region of another of the first and second capacitors;
- wherein the first and second capacitors in series are configured to discharge the capacitive storage element;
- and
- wherein outputs from the first and second comparator provide a binary word indicative of a duration that has elapsed from a start of an operation of discharging the capacitive storage element.
12 more elements
An integrated circuit, comprising:
- a semiconductor substrate having a front face;
- a trench extending into the semiconductor substrate from the front face;
- a first conductive region housed in the trench and insulated from the semiconductor substrate by an insulating liner;
- a dielectric layer extending over the front face of the semiconductor substrate and further extending at least partially over the first conductive region in the trench;
- wherein the dielectric layer has a thickness allowing charge to flow by direct tunneling effect;
- a second conductive region on the dielectric layer;
- wherein the first conductive region in the trench, the dielectric layer and the second conductive region form a capacitor;
- a semiconductor well that is housed in the semiconductor substrate;
- a first contact and a second contact which are electrically connected by an electrical path through the semiconductor well, wherein said electrical path comprises a section of said semiconductor well that is located underneath a bottom of the trench;
- and
- a detection circuit configured to detect an electrical discontinuity in the semiconductor well between the first contact and the second contact.
8 more elements
Dependencies are inferred from the claim text.