Stress compensation for wafer to wafer bonding

A computing device, comprising:

• a first wafer;
• a second wafer bonded to the first wafer by wafer bonding, wherein the first wafer or the second wafer includes a processor or a memory device;
• and
• a stress compensation layer between the first wafer and the second wafer, and in contact with both the first wafer and the second wafer, wherein:
• the first wafer has a first stress level at a first location of the first wafer, and a second stress level at a second location of the first wafer, where the second stress level is different from the first stress level;
• and
• the stress compensation layer includes a first material at a first location of the stress compensation layer overlapping with the first location of the first wafer, a second material at a second location of the stress compensation layer overlapping with the second location of the first wafer, the stress compensation layer induces a third stress level at the first location of the first wafer, and a fourth stress level at the second location of the first wafer,
• the first wafer has a sum stress level of the first location equal to the first stress level and the third stress level, and a sum stress level of the second location equal to the second stress level and the fourth stress level, the sum stress level of the first location is substantially same as the sum stress level of the second location.