Comparator with negative capacitance compensation

A circuit comprising:

• an amplifier portion having a first input coupled to receive a first analog signal and a first output, the amplifier portion coupled between a first voltage supply terminal and the first output;
• a first current source coupled to the first voltage supply terminal and configured to generate a first current for the amplifier portion;
• a latch portion coupled to the amplifier portion at the first output, the latch portion configured to provide a digital value based on the first analog signal;
• a negative capacitance portion coupled to the amplifier portion and the latch portion at the first output, the negative capacitance portion configured to cancel parasitic capacitance coupled at the first output;
• a second current source coupled to the first voltage supply terminal and configured to generate a second current substantially one-half of the first current for the negative capacitance portion;
• and
• a first digital-to-analog converter (DAC) having an input coupled to the first output in a first feedback loop, an output of the DAC coupled to provide a second analog signal representative of the digital value.

A circuit comprising:

• an amplifier portion comprising:
• a first transistor having a first current electrode, a second current electrode coupled to a first output, and a control electrode coupled to receive a first analog signal, and
• a second transistor having a first current electrode coupled to the first current electrode of the first transistor, a second current electrode coupled to a second output, and a control electrode coupled to receive a second analog signal, the first analog signal and the second analog signal together comprising a differential signal;
• a first current source having a first terminal coupled to a first voltage supply terminal and a second terminal coupled to the first current electrode of the first and second transistors, the first current source configured to generate a first current;
• a latch portion coupled to the amplifier portion, the latch portion comprising:
• a third transistor having a first current electrode coupled at the second output and a control electrode coupled at the first output, and
• a fourth transistor having a first current electrode coupled at the first output and a control electrode coupled at the second output;
• a negative capacitance portion coupled to the amplifier portion and the latch portion, the negative capacitance portion comprising:
• a fifth transistor having a first current electrode coupled at the first output and a control electrode coupled at the second output,
• a sixth transistor having a first current electrode coupled at the second output and a control electrode coupled at the first output,
• a capacitor having a first terminal coupled to a second current electrode of the first transistor and a second terminal coupled to a second current electrode of the second transistor;
• and
• a second current source having a first terminal coupled to the first voltage supply terminal and a second terminal coupled to the second current electrode of the fifth transistor, the second current source configured to generate a second current substantially one-half of the first current;
• and
• a digital-to-analog converter (DAC) having an input coupled to the first output in a first feedback loop, an output of the DAC coupled to provide a second analog signal representative of the digital value.