Adder circuit using lookup tables

A computer-readable medium containing instructions that when executed by a machine, cause the machine to program a field programmable gate array (FPGA) to generate a circuit comprising:

• a first two-bit arithmetic logic unit (ALU) slice comprising:
• a plurality of four-input lookup tables (LUT4s) including a first LUT4 and a second LUT4;
• input connections configured to receive as input two bits of a first operand, two bits of a second operand, a first carry-in bit from a second two-bit ALU slice, and a second carry-in bit from a third two-bit ALU slice;
• a multiplexer controlled by the second carry-in bit;
• and
• output connections configured to provide, as output, two sum bits and a carry-out bit, the two sum bits containing the sum of the input two bits of the first operand, the input two bits of the second operand, and the first carry-in bit;
• wherein:
• each of the plurality of LUT4s receives the two bits of the first operand and the two bits of the second operand as inputs;
• the first LUT4 is configured to generate an output that is a binary exclusive or (XOR) of a low bit of the first operand with a low bit of the second operand;
• and
• a high order bit of the sum bits is an XOR of the output of the second LUT4 of the plurality of LUT4s with the output of the multiplexer.

A system comprising:

• a memory that stores instructions;
• and
• one or more processors configured by the instructions to perform operations comprising:
• programming a field programmable gate array (FPGA) to generate a circuit comprising:
• a first two-bit arithmetic logic unit (ALU) slice comprising:
• a plurality of four-input lookup tables (LUT4s) including a first LUT4 and a second LUT4;
• input connections configured to receive as input two bits of a first operand, two bits of a second operand, a carry-in bit from a second two-bit ALU slice, and a second carry-in bit from a third two-bit ALU slice;
• a multiplexer controlled by the second carry-in bit;
• and
• output connections configured to provide, as output, two sum bits and a carry-out bit, the two sum bits containing the sum of the input two bits of the first operand, the input two bits of the second operand, and the first carry-in bit;
• wherein:
• each of the plurality of LUT4s receives the two bits of the first operand and the two bits of the second operand as inputs;
• the first LUT4 is configured to generate an output that is a binary exclusive or (XOR) of a low bit of the first operand with a low bit of the second operand;
• and
• a high order bit of the sum bits is an XOR of the output of the second LUT4 of the plurality of LUT4s with the output of the multiplexer.