Device and method for binary flag determination

A first circuit comprising:

• an arithmetic and logic unit (ALU) circuit, comprising:
• an arithmetic operations circuit configured to:
• add a second masked datum and a third masked datum to obtain a first masked binary datum;
• process the first masked binary datum;
• and
• provide the first masked binary datum to a flag generator circuit;
• and
• the flag generator circuit, comprising:
• three comparator circuits configured to receive two masked data, corresponding masks for the two masked data, an addition/subtraction selection bit, the first masked binary datum, and a corresponding first mask for the first masked binary datum;
• and
• an EXCLUSIVE OR logic gate coupled to the three comparator circuits and the arithmetic operations circuit, and configured to determine a carry digit indicator bit of the first masked binary datum, without unmasking the first masked binary datum, by one of the following formulas:
• Flag_C=CD1_M xor CD2_M xor CADD_D_M xor CADD_MD xor CD_M;
• or
• Flag_C=CD1_M+CD2_M+CADD_D_M−CADD_MD−CD_M
• where:
• Flag_C represents the carry digit indicator bit;
• “xor” represents an EXCLUSIVE OR logic operation;
• “+” represents an addition operation;
• “−” represents a subtraction operation;
• CD1_M represents a first carry digit that may appear during a masking operation leading to the second masked datum;
• CD2_M represents a second carry digit that may appear during the masking operation leading to the third masked datum;
• CADD_D_M represents a third carry digit that may appear during the addition of the second masked datum and the third masked datum;
• CADD_MD represents a fourth carry digit that may appear during an addition of a second mask and a third mask;
• and
• CD_M represents a fifth carry digit that may appear during the masking operation leading to the first masked binary datum.

An arithmetic and logic unit (ALU) circuit in a central processing unit (CPU) comprising:

• five inputs, of the ALU circuit in the CPU, configured to receive two masked data, associated masks for the two masked data, and an addition/subtraction selection bit;
• an arithmetic operations circuit coupled to the five inputs, and configured to:
• add or subtract the two masked data, and add or subtract the associated masks for the two masked data, in accordance with the addition/subtraction selection bit, and
• generate a masked datum and an associated mask for the masked datum;
• three comparator circuits coupled to the five inputs, the masked datum, and the associated mask for the masked datum;
• and
• an EXCLUSIVE OR logic gate coupled to outputs of the three comparator circuits and the arithmetic operations circuit, and configured to generate a carry digit indicator bit without unmasking the two masked data or the masked datum.