Method and apparatus for testing artificial intelligence chip, device and storage medium

An electronic device, comprising:

• at least one processor;
• and
• a memory communicatively connected to the at least one processor;
• wherein, the memory stores instructions executable by the at least one processor, and the at least one processor when executing the instructions is configured to:
• obtain scale information of a target artificial intelligence chip;
• determine whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information;
• divide all the arithmetic units into multiple same arithmetic unit arrays, and perform a Design for Test (DFT) test on the arithmetic unit arrays, respectively, upon determining that the test condition of the arithmetic unit array level is satisfied, wherein the performing the DFT test on the arithmetic unit arrays comprises performing, at the arithmetic unit array level, the DFT test on each of the arithmetic unit arrays;
• perform the DFT test on the arithmetic units, respectively, upon determining that the test condition of the arithmetic unit array level is not satisfied, wherein the performing the DFT test on the arithmetic units comprises performing, at an arithmetic unit level, the DFT test on each of the arithmetic units;
• wherein the scale information comprises a number of transistors in an arithmetic unit, and the at least one processor is further configured to:
• determine whether the number of the transistors is smaller than a preset scale threshold;
• determine the test condition of the arithmetic unit array level is satisfied, upon determining that the number of the transistors is less than the preset scale threshold;
• determine the test condition of the arithmetic unit array level is not satisfied, upon determining that the number of the transistors is greater than or equal to the preset scale threshold.

A non-transitory computer-readable storage medium having computer instructions stored thereon, wherein the computer instructions are used to cause a computer to perform a method comprising:

• obtaining scale information of a target artificial intelligence chip;
• determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information;
• dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a Design for Test (DFT) test on the arithmetic unit arrays, respectively, upon determining that the test condition of the arithmetic unit array level is satisfied, wherein the performing the DFT test on the arithmetic unit arrays comprises performing, at the arithmetic unit array level, the DFT test on each of the arithmetic unit arrays;
• performing the DFT test on the arithmetic units, respectively, upon determining that the test condition of the arithmetic unit array level is not satisfied, wherein the performing the DFT test on the arithmetic units comprises performing, at an arithmetic unit level, the DFT test on each of the arithmetic units;
• wherein the scale information comprises a number of transistors in an arithmetic unit, and the determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information, comprises:
• determining whether the number of the transistors is smaller than a preset scale threshold;
• determining the test condition of the arithmetic unit array level is satisfied, upon determining that the number of the transistors is less than the preset scale threshold;
• determining the test condition of the arithmetic unit array level is not satisfied, upon determining that the number of the transistors is greater than or equal to the preset scale threshold.