High accuracy time stamping for multi-lane ports

A method for adjusting a time stamp of a packet, the method comprising:

• receiving a packet over multiple lanes, wherein the packet comprises an Ethernet frame compatible with IEEE 802.3-2018 and one of the multiple lanes includes packet start information;
• adjusting a time stamp associated with the received packet based on packet start information received in a particular lane and based on serializer/de-serializer time delay, wherein the adjusted time stamp is to provide sub-nanosecond time stamp accuracy and the packet start information comprises a start of frame delimiter (SFD) compatible with IEEE 1588-2008;
• and
• providing the adjusted time stamp as an output.

A system comprising:

• physical medium attachment (PMA) circuitry comprising at least one serializer/de-serializer circuitry to receive a packet and perform de-serialization of the received packet;
• physical coding sublayer (PCS) circuitry to perform bit width transformation on the de-serialized received packet;
• and
• circuitry to receive the de-serialized received packet over multiple lanes from the PCS circuitry, wherein one of the multiple lanes includes packet start information;
• circuitry to adjust a time stamp associated with the received packet based on packet start information received in a particular lane and based on time delay of the at least one serializer/de-serializer circuitry;
• and
• circuitry to provide the adjusted time stamp as an output, wherein:
• the adjusted time stamp is to provide sub-nanosecond time stamp accuracy,
• the packet comprises an Ethernet frame compatible with IEEE 802.3-2018 and
• the packet start information comprises a start of frame delimiter (SFD) compatible with IEEE 1588-2008.