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US 11,710,729 B2Granted
Wafer bonding in fabrication of 3-dimensional NOR memory circuits
AssigneeSunrise Memory Corporation
InventorsScott Brad Herner, Eli Harari
Life of this patent
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Abstract
A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of a interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.
Claims15
A memory integrated circuit, comprising:
- a first semiconductor wafer, comprising (i) a monocrystalline semiconductor substrate (“first substrate”) having first and second planar surface (“first obverse surface” and “first reverse surface”, respectively), (ii) circuitry for supporting memory operations (“first circuitry”) formed in the first substrate or at the first obverse surface;
- (iii) a memory circuit, formed above the first obverse surface, comprising an array of thin-film storage transistors that are electrically connected to and configured to be operated at least in part by the first circuitry;
- and (iv) a plurality of interconnect conductors (“first interconnect conductors”) formed above the memory circuit and electrically connected to the memory circuit;
- and
- a second semiconductor wafer, comprising (i) a monocrystalline semiconductor substrate (“second substrate”) having first and second planar surfaces (“second obverse surface” and “second reverse surface”, respectively), (ii) circuitry for supporting memory operations (“second circuitry”) formed in the second substrate or at the second obverse surface;
- and (iii) a plurality of interconnect conductors (“second interconnect conductors”) formed above the second circuitry, and electrically connected to the second circuitry;
- wherein the first and second semiconductor wafers are joined by wafer-bonding at the first and the second interconnect conductors, such that the second circuitry is electrically connected through the first and the second interconnect conductors to the memory circuit, thereby allowing the second circuitry to operate, at least in part, the memory circuit.
4 more elements
Dependencies are inferred from the claim text.