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US 11,707,003 B2Granted
Memory device and manufacturing method thereof
AssigneeUnited Microelectronics Corp.
InventorsChich-Neng Chang, Da-Jun Lin, Shih-Wei Su, Fu-Yu Tsai, Bin-Siang Tsai
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Abstract
A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.
Claims13
A memory device, comprising:
- a device substrate;
- a bottom electrode, disposed on the device substrate;
- a resistance variable layer, disposed on the bottom electrode;
- and
- a top electrode, disposed on the resistance variable layer,
- wherein the bottom electrode is formed with a tensile stress, and the top electrode is formed with a compressive stress.
3 more elements
A memory device, comprising:
- a bottom electrode with a first stress and a top electrode with a second stress, formed in a back-end-of-line (BEOL) structure over a semiconductor substrate, wherein the top electrode is located over the bottom electrode, and overlapped with the bottom electrode;
- and
- a resistance variable layer, sandwiched between the bottom electrode and the top electrode, and subjected to a compressive strain generated by the first stress of the bottom electrode and the second stress of the top electrode;
- wherein a direction of the first stress and a direction of the second stress are not parallel to the interfaces between the bottom electrode and the resistance variable layer and between the top electrode and the resistance variable layer.
1 more element
Dependencies are inferred from the claim text.