Memory cells
AssigneeMicron Technology, Inc.
InventorsKamal M. Karda, Qian Tao, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Kirk D. Prall, Ashonita Chavan
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Abstract
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.
Claims17
A memory array comprising a plurality of memory cells, each of the memory cells comprising:
- a select device;
- and
- a capacitor coupled to the select device, the capacitor comprising a first electrode and a second electrode, the capacitor having a first current leakage path between the first electrode and the second electrode through ferroelectric material, the capacitor having a second current leakage path between the first electrode and the second electrode through an amorphous semiconducting material, the ferroelectric material comprising one or more materials selected from the group consisting of zirconium, zirconium oxide, hafnium, barium strontium titanate, HfxSiyOz and HfxZryOz, wherein the one or more materials is optionally doped with a dopant comprising one or more member of the group consisting of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium and rare earth elements.
A memory system comprising:
- a plurality of memory cells, each memory cell of the plurality comprising:
- a capacitor comprising two conductive capacitor electrodes having ferroelectric material there-between, the capacitor comprising an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material;
- and
- a parallel current leakage path from the one capacitor electrode to the other, the parallel current leakage path being circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path, the parallel current leakage path not being directly against the ferroelectric material, the parallel current leakage path comprising a non-linear resistor between the two capacitor electrodes exhibiting higher resistance at higher voltages than at lower voltages.
A memory system comprising an array of memory cells, at least some of the memory cells comprised by the array each comprising:
- a capacitor comprising two conductive capacitor electrodes having ferroelectric material there-between, the capacitor comprising an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material;
- and
- a parallel current leakage path from the one capacitor electrode to the other, the parallel current leakage path being circuit-parallel the intrinsic current leakage path, the parallel current leakage path having a dominant band gap of 0.4 eV to 5.0 eV, the parallel current leakage path not being directly against the ferroelectric material, the parallel current leakage path predominantly comprises one or more of amorphous silicon and germanium.
Dependencies are inferred from the claim text.