US 11,706,927 B2Granted

Memory devices and methods of forming memory devices

AssigneeMicron Technology, Inc.

InventorsGiorgio Servalli, Marcello Mariani

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Abstract

Some embodiments include an integrated assembly having pillars arranged in an array. The pillars have channel regions between upper and lower source/drain regions. Gating structures are proximate to the channel regions and extend along a row direction. Digit lines are beneath the pillars, extend along a column direction, and are coupled with the lower source/drain regions. Linear structures are above the pillars and extend along the column direction. Bottom electrodes are coupled with the upper source/drain regions. The bottom electrodes have horizontal segments adjacent the upper source/drain regions and have vertical segments extending upwardly from the horizontal segments. The vertical segments are adjacent to lateral sides of the linear structures. Ferroelectric-insulative-material and top-electrode-material are over the bottom electrodes. A slit passes through the top-electrode-material, is directly over one of the linear structures, and extends along the column direction.

Claims35

Dependent claims

An integrated assembly, comprising:

a first memory cell comprising a first pillar of a semiconductor material;
the first pillar comprising a first upper source/drain region and a first channel region under the first upper source/drain region;
a second memory cell comprising a second pillar of the semiconductor material;
the second pillar comprising a second upper source/drain region and a second channel region under the second upper source/drain region;
a gating structure passing along the first channel region and the second channel region and comprising regions proximate the first channel region and the second channel region, the gating structure extending along a first direction;
an insulative structure over regions of the first pillar and the second pillar, the insulative structure extending along a second direction which is orthogonal to the first direction;
a first bottom electrode electrically coupled with the first upper source/drain region, and a second bottom electrode electrically coupled with the second upper source/drain region;
the first bottom electrode and the second bottom electrode being configured as a first angle plate and a second angle plate, respectively;
the second angle plate being a mirror image of the first angle plate;
the first angle plate and the second angle plate having horizontal segments adjacent to the first upper source/drain region and the second upper source/drain region, respectively;
and having vertical segments extending upwardly from the horizontal segments;
the vertical segments of the first angle plate and the second angle plate being adjacent to lateral sides of the insulative structure;
ferroelectric-insulative-material over the first bottom electrode and the second bottom electrode;
top-electrode-material over the ferroelectric-insulative-material;
and
a slit passing through the top-electrode-material and extending along the second direction;
the slit being directly over the insulative structure.

14 more elements

An integrated assembly, comprising:

pillars arranged in an array;
the array comprising a row direction and a column direction;
the pillars having upper source/drain regions, lower source/drain regions, and channel regions between the upper source/drain regions and the lower source/drain regions;
gating structures proximate the channel regions and extending along the row direction;
conductive structures beneath the pillars and electrically coupled with the lower source/drain regions;
the conductive structures extending along the column direction;
insulative structures above the pillars and extending along the column direction;
each of the insulative structures having a first lateral side and an opposing second lateral side, and being associated with the pillars along the first lateral side and the opposing second lateral side;
bottom electrodes electrically coupled with the upper source/drain regions;
the bottom electrodes being configured as angle plates;
the angle plates having horizontal segments adjacent to the upper source/drain regions and having vertical segments extending upwardly from the horizontal segments;
the vertical segments being adjacent to the first lateral side and the opposing second lateral side of the insulative structures;
the bottom electrodes including a first set adjacent to the first lateral sides and a second set adjacent to the opposing second lateral sides;
the first set of the bottom electrodes having the horizontal segments projecting in a first direction from the vertical segments;
the second set of the bottom electrodes having the horizontal segments projecting in a second direction from the vertical segments;
the second direction being opposite to the first direction and parallel to the row direction;
ferroelectric-insulative-material over the bottom electrodes;
top-electrode-material over the ferroelectric-insulative-material;
and
one or more slits passing through the top-electrode-material and extending along the column direction;
each of said one or more slits being directly over an associated one of the insulative structures.

18 more elements

An integrated assembly, comprising:

pillars arranged in an array;
the array comprising a row direction and a column direction;
the pillars having upper source/drain regions, lower source/drain regions, and channel regions between the upper source/drain regions and the lower source/drain regions;
shield lines extending along the row direction and being in regions between the pillars;
gating structures proximate the channel regions and extending along the row direction;
conductive structures beneath the pillars and electrically coupled with the lower source/drain regions;
the conductive structures extending along the column direction;
linear structures above the pillars and extending along the column direction;
each of the linear structures having a first lateral side and an opposing second lateral side, and being associated with the pillars along the first lateral side and the opposing second lateral side;
bottom electrodes electrically coupled with the upper source/drain regions;
the bottom electrodes having first segments adjacent to the upper source/drain regions and having second segments extending upwardly from the first segments;
the second segments being adjacent to the first lateral side and the opposing second lateral side of the linear structures;
the bottom electrodes including a first set along to the first lateral sides and a second set along to the opposing second lateral sides;
the bottom electrodes of the first set having the first segments projecting from the second segments in a first direction;
of the bottom electrodes of the second set having the first segments projecting from the second segments in a second direction which is opposite to the first direction and parallel to the row direction;
ferroelectric-insulative-material over the bottom electrodes;
top-electrode-material over the ferroelectric-insulative-material;
and
one or more slits passing through the top-electrode-material and extending along the column direction;
each of said one or more slits being directly over an associated one of the linear structures.

17 more elements

A method of forming an integrated assembly, comprising:

forming a construction having an array of pillars of a semiconductor material;
the array comprising rows and columns;
the pillars having upper source/drain regions, lower source/drain regions, and channel regions between the upper source/drain regions and the lower source/drain regions;
the construction including gating structures extending along a row direction and being proximate the channel regions, and including conductive structures extending along a column direction orthogonal to the row direction and being coupled with the lower source/drain regions;
the construction including a first insulative material between the upper source/drain regions of the pillars;
an upper surface of the construction extending across the first insulative material and across upper surfaces of the upper source/drain regions;
forming linear structures over the upper surface of the construction and extending along the column direction;
each of the linear structures having a first lateral side and an opposing second lateral side, and being associated with the pillars along the first lateral side and the opposing second lateral side;
forming bottom-electrode-material along the linear structures and along regions of the upper surface of the construction between the linear structures;
patterning the bottom-electrode-material into bottom-electrode-structures;
the bottom-electrode-structures having first segments along the upper surfaces of the upper source/drain regions and having second segments along the sidewalls of the linear structures;
forming ferroelectric-insulative-material over the bottom-electrode-structures;
forming top-electrode-material over the ferroelectric-insulative-material;
and
forming one or more slits to pass through the top-electrode-material;
said one or more slits extending along the column direction and being directly over one or more of the linear structures;
said one or more slits dividing the top-electrode-material into two or more plates.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/189,594Filed 2 Mar 2021
Published: US 2022/0285392 A18 Sep 2022
Granted: 18 Jul 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 51/20
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the three-dimensional [3D] arrangements, e.g. with…
H10D 1/716
Having non-planar surfaces, e.g. formed by texturisation: having vertical extensions
H10B 51/10
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the top-view layout
H10B 53/10
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the top-view layout