Method of forming an array boundary structure to reduce dishing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Han Lin, Te-Hsin Chiu, Wei-Cheng Wu, Li-Feng Teng, Chien-Hung Chang
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Abstract
A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
Claims20
A method of fabricating a semiconductor structure, comprising:
- providing a semiconductor substrate comprising a semiconductor portion;
- forming a first trench isolation structure (TIS) and a second TIS inset into the semiconductor substrate respectively at a first region and a second region, wherein the first TIS and the second TIS are separated by and border the semiconductor portion, and wherein the second TIS surrounds the first TIS;
- forming a first device on the first region and surrounded by the first TIS;
- forming a second device and a first dummy ring on the second region, wherein the first dummy ring surrounds the first device directly over the second TIS, and wherein the second TIS separates the second device from the semiconductor portion;
- forming a dielectric layer on the semiconductor substrate to cover the first device, the second device, and the first dummy ring;
- and
- polishing the dielectric layer until the first device, the second device, and the first dummy ring are exposed.
A method of fabricating a semiconductor structure, comprising:
- forming a first trench isolation structure (TIS) and a second TIS inset into a semiconductor substrate;
- forming a first device and a second device, wherein the first TIS and the second TIS are spaced from and between the first and second devices;
- forming a first dummy ring and a second dummy ring surrounding the first device, wherein the first dummy ring is directly over the second TIS and the second dummy ring is directly over the first TIS;
- depositing a contact etch stop layer (CESL) covering the first and second dummy rings;
- depositing an interlayer dielectric (ILD) layer covering the CESL;
- and
- performing a first polishing process into the ILD layer to clear the ILD layer from atop the first and second dummy rings;
- wherein the CESL persists at covering the first and second dummy rings upon completion of the first polishing process, and wherein the ILD layer has a slanted surface, which slants downward towards the second device and has a top edge directly over the second TIS, upon completion of the first polishing process.
A method of fabricating a semiconductor structure, comprising:
- forming a trench isolation structure (TIS) recessed into a substrate;
- forming a first device over the substrate;
- depositing a dielectric layer covering the TIS and the substrate over the first device;
- forming a first dummy pattern and a plurality of dummy dot patterns directly over the TIS and the dielectric layer, wherein the first dummy pattern is ring shaped and surrounds the first device, and wherein the dummy dot patterns are in a ring shape around the first device;
- and
- performing an etch into the dielectric layer with the first dummy pattern and the plurality of dummy dot patterns in place to form a first dielectric pattern and a plurality of dielectric dot patterns respectively underlying the first dummy pattern and the plurality of dummy dot patterns.
Dependencies are inferred from the claim text.