Semiconductor devices

A semiconductor device comprising:

• an active pattern on a substrate;
• a gate structure in an upper portion of the active pattern;
• a bit line structure on the active pattern, the bit line structure including a first conductive pattern, a diffusion barrier, a second conductive pattern and a capping pattern sequentially stacked on the substrate;
• a lower spacer structure extending on a portion of a sidewall of the first conductive pattern of the bit line structure;
• an upper spacer structure on the lower spacer structure, the upper spacer structure extending on a portion of a sidewall of the bit line structure;
• a contact plug structure on the active pattern adjacent to the bit line structure;
• and
• a capacitor on the contact plug structure,
• wherein the first conductive pattern includes polysilicon doped with n-type impurities, and the second conductive pattern includes metal,
• wherein the lower spacer structure includes a first lower spacer and a second lower spacer sequentially stacked on the portion of the sidewall of the first conductive pattern of the bit line structure, the first lower spacer contacts the portion of the sidewall of the first conductive pattern and includes oxide, and the second lower spacer includes nitride,
• wherein the first lower spacer does not contact the portion of the sidewall of the bit line structure, and a portion of the upper spacer structure contacts the portion of the sidewall of the bit line structure and includes nitride, and
• wherein the first lower spacer comprises opposite end portions and a middle portion that continuously extends between the opposite end portions of the first lower spacer, and both of the opposite end portions of the first lower spacer contact the upper spacer structure.

A semiconductor device comprising:

• an active pattern on a substrate;
• a gate structure in an upper portion of the active pattern;
• a bit line structure on the active pattern, the bit line structure including a first conductive pattern, a second conductive pattern and a capping pattern sequentially stacked on the substrate;
• a first spacer on a sidewall of the first conductive pattern, the first spacer including silicon oxide;
• a second spacer extending on an outer sidewall of the first spacer and sidewalls of the second conductive pattern and the capping pattern, at least a portion of the second spacer and the first spacer being stacked in a horizontal direction substantially parallel to an upper surface of the substrate;
• a third spacer and a fourth spacer sequentially stacked on a lower portion of an outer sidewall of the second spacer;
• a fifth spacer and a sixth spacer sequentially stacked on an upper portion of the outer sidewall of the second spacer;
• a contact plug structure on the active pattern adjacent to the bit line structure;
• and
• a capacitor on the contact plug structure.