Integrated assemblies comprising memory cells and shielding material between the memory cells

A memory array, comprising:

• a semiconductor material having a horizontal surface;
• vertically-extending semiconductor pillars over the horizontal surface;
• each of the semiconductor pillars comprising a transistor channel region vertically disposed between a first source/drain region and a second source/drain region;
• the semiconductor pillars being arranged in rows and columns of the memory array;
• the rows extending along a row direction, and the columns extending along a column direction;
• wordlines extending along the row direction;
• the wordlines being adjacent the transistor channel regions of the semiconductor pillars;
• each row of the memory array including a plurality of the semiconductor pillars along an associated one of the wordlines;
• said associated one of the wordlines having a first lateral surface and an opposing second lateral surface;
• the plurality of semiconductor pillars associated with said one of the wordlines being subdivided amongst a first set along the first lateral surface, and a second set along the second lateral surface;
• the semiconductor pillars of the first set being spaced from said associated one of the wordlines by a gate dielectric material between the first lateral surface and the transistor channel regions of the semiconductor pillars of the first set;
• the semiconductor pillars of the second set being spaced from said associated one of the wordlines by the gate dielectric material between the second lateral surface and the transistor channel regions of the semiconductor pillars of the second set;
• conductive shield material between the semiconductor pillars;
• bitlines extending along the column direction and being coupled with the first source/drain regions;
• and
• storage elements being coupled with the second source/drain regions;
• each of the storage elements being uniquely addressed by one of the wordlines in combination with one of the bitlines.