Image sensor with voltage supply grid clamping

An image sensing device, comprising:

• an image sensing circuit including a plurality of pixels arranged in a plurality of rows and a plurality of columns;
• a voltage supply grid coupled to the plurality of pixels;
• a plurality of bitlines, wherein each one of the plurality of bitlines is coupled to a corresponding one of the plurality of columns;
• and
• a control circuit coupled to output at least a row select signal and a transfer signal to each one of the plurality of rows, wherein the control circuit includes:
• an address decoder coupled to generate a row enable signal in response to an address signal;
• a latch coupled to receive the row enable signal, a clear clamp signal, and a set clamp signal;
• a first AND gate is coupled to receive the row enable signal an active row RS enable signal;
• a second AND gate is coupled to receive an output of the latch and an ECL signal enable signal;
• a tri-state buffer coupled to receive a level shifted output of the first AND gate and a level shifted output of the second AND gate;
• and
• a switch coupled having a drain coupled to a clamp voltage, a gate coupled to receive the level shifted output of the first AND gate, and a source coupled to an output of the tri-state buffer, wherein the row select signal is coupled to be generated at the output of the tri-state buffer,
• wherein each one of the plurality of rows is selectively coupled to the plurality of bitlines to selectively output image data signals in response to the row select signal and the transfer signal,
• wherein each one of the plurality of rows is further selectively coupled to the plurality of bitlines to selectively clamp the plurality of bitlines in response to the row select signal and the transfer signal, and
• wherein each one of the plurality of rows is selectively decoupled from the plurality of bitlines in response to the row select signal.

An image sensing device, comprising:

• a plurality of bitlines;
• a plurality of pixels, wherein each of the plurality of pixels includes a row select transistor, wherein the row select transistor includes a first terminal and a second terminal, wherein the first terminal is a gate of the row select transistor, wherein the second terminal is connected to one of the plurality of bitlines;
• a control circuit coupled to control the plurality of pixels;
• and
• a voltage supply grid coupled to the plurality of pixels,
• wherein each one of the plurality of pixels is coupled to selectively output an image data signal to said one of the plurality of bitlines,
• wherein each one of the plurality of pixels is further coupled to selectively clamp said one of the plurality of bitlines,
• wherein each one of the plurality of pixels is arranged to selectively decouple from said one of the plurality of bitlines,
• wherein the control circuit is coupled to cause a clamp voltage to be applied to the first terminal of the row select transistor while an on voltage is applied to a first terminal of a row select transistor of another one of the plurality of pixels coupled to said one of the plurality of bitlines to control the pixel to selectively clamp said one of the plurality of bitlines such that a clamp current passes through the second terminal, and
• wherein the clamp voltage that is applied to the first terminal of the row select transistor is between the on voltage for the first terminal of the row select transistor and an off voltage for the first terminal of the row select transistor.

An image sensing device, comprising:

• a plurality of bitlines;
• a plurality of pixels, wherein each of the plurality of pixels includes a row select transistor, wherein the row select transistor includes a first terminal and a second terminal, wherein the second terminal is connected to one of the plurality of bitlines;
• a control circuit coupled to control the plurality of pixels, wherein the control circuit includes:
• an address decoder coupled to generate a row enable signal in response to an address signal;
• a latch coupled to receive the row enable signal, a clear clamp signal, and a set clamp signal;
• a first AND gate is coupled to receive the row enable signal an active row RS enable signal;
• a second AND gate is coupled to receive an output of the latch and an ECL signal enable signal;
• a tri-state buffer coupled to receive a level shifted output of the first AND gate and a level shifted output of the second AND gate;
• and
• a switch coupled having a drain coupled to a clamp voltage, a gate coupled to receive the level shifted output of the first AND gate, and a source coupled to an output of the tri-state buffer, wherein the row select signal is coupled to be generated at the output of the tri-state buffer;
• and
• a voltage supply grid coupled to the plurality of pixels,
• wherein each one of the plurality of pixels is coupled to selectively output an image data signal to said one of the plurality of bitlines,
• wherein each one of the plurality of pixels is further coupled to selectively clamp said one of the plurality of bitlines,
• wherein each one of the plurality of pixels is arranged to selectively decouple from said one of the plurality of bitlines,
• wherein the control circuit is coupled to cause a clamp voltage to be applied to the first terminal of the row select transistor to control the pixel to selectively clamp said one of the plurality of bitlines such that a clamp current passes through the second terminal.