Information processing apparatus and method of notifying verification result of program
AssigneeCanon Kabushiki Kaisha
InventorShinichi Ono
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AssigneeCanon Kabushiki Kaisha
InventorShinichi Ono
Estimating the term…
An information processing apparatus includes a control unit, a storage unit configured to store a program to be executed by the control unit, a verification unit configured to read the program from the storage unit and to verify the read program, and a light-emitting unit configured to be changed to a predetermined light-emitting state or to be changed from the predetermined light-emitting state based on a result of the verification of the program by the verification unit.
An information processing apparatus configured to verify whether a program is valid and execute a program that has been verified to be valid, the information processing apparatus comprising:
Dependencies are inferred from the claim text.
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Power supply means, e.g. arrangements for the control of power supply to the apparatus or components thereof: detection of supply level or supply…
Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates…:…
Control thereof: switching on or off, e.g. for saving power when not in use
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The present disclosure relates to an information processing apparatus and the like that verifies a program that a control unit executes.
As a method of detecting falsification of a boot code in an image forming apparatus (hereinafter, referred to as multifunctional peripheral (MFP)), there is a method in which a sub-central processing unit (CPU) loads a boot code to be executed by a main CPU before startup of the main CPU, and verifies whether the loaded boot code has not been falsified. As processing performed in a case where the sub-CPU detects falsification of the boot code, a method in which the sub-CPU controls a reset signal that is input to the main CPU in order to prevent startup of the main CPU, to maintain a reset state of the main CPU, is conceivable.
Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2011-511331 discusses the technique of determining whether a first component has been falsified, and when the first component has not been falsified, booting of the first component is started to update state information so as to indicate success of the booting, whereas when the first component has been falsified, booting of the first component is prevented.
FIG. 1 is a diagram illustrating a configuration of a multifunctional peripheral (MFP).
FIG. 2 is a diagram illustrating a configuration of a main central processing unit (CPU).
FIG. 3 is a diagram illustrating a configuration of a sub-CPU.
A first exemplary embodiment of the present disclosure is described below with reference to drawings.
A multifunctional peripheral (MFP) is described as an example of an information processing apparatus that executes a failure detection method when validity of a boot code (boot program) of a main central processing unit (CPU) 101 is verified (when processing to detect falsification of boot code is performed). The MFP is an image forming apparatus (printing apparatus) including an image forming function (print function). Unless otherwise noted, the present disclosure is applicable to a single apparatus as well as a system including a plurality of apparatuses as long as functions according to the present exemplary embodiment are executed.
FIG. 1 is a diagram illustrating a configuration of an MFP 1. In FIG. 1, the main CPU 101 serves as a first control unit that controls the whole of the MFP 101.