Incremental analog-to-digital converter and circuit system using the same
AssigneeNuvoton Technology Corporation
InventorChung Ming Hsieh
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Abstract
An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.
Claims17
An incremental analog-to-digital converter, comprising:
- a conversion circuit configured to perform incremental analog-to-digital conversion, and comprising a plurality of integrator modules and a feedback module;
- and
- a reset signal processing module configured to receive a first reset signal, and generate a second reset signal based on the first reset signal, wherein starting time points of the first reset signal and the second reset signal are the same, an ending time point of the second reset signal is later than an ending time point of the first reset signal by at least one clock cycle;
- wherein a first-stage integrator module of the plurality of integrator modules is reset by the second reset signal, and the other of the plurality of integrator modules and the feedback module are reset by the first reset signal.
An incremental analog-to-digital converter, comprising:
- a conversion circuit configured to perform incremental analog-to-digital conversion, and comprising a plurality of memorization elements, wherein the plurality of memorization elements comprise a first-stage non-delay memorization element;
- and
- a reset signal processing module configured to receive a first reset signal, and generate a second reset signal based on the first reset signal, wherein starting time points of the first reset signal and the second reset signal are the same, and an ending time point of the second reset signal is later than an ending time point of the first reset signal by at least one clock cycle;
- wherein the first-stage non-delay memorization element is reset by the second reset signal, and the other of the plurality of memorization elements is reset by the first reset signal.
A circuit system comprising:
- a signal acquisition device;
- an incremental analog-to-digital converter electrically connected to the signal acquisition device;
- and
- a processing device electrically connected to the incremental analog-to-digital converter;
- wherein the incremental analog-to-digital converter comprises:
- a conversion circuit configured to perform incremental analog-to-digital conversion, and comprising a plurality of integrator modules and a feedback module;
- and
- a reset signal processing module configured to receive a first reset signal, and generate a second reset signal based on the first reset signal, wherein starting time points of the first reset signal and the second reset signal are the same, an ending time point of the second reset signal is later than an ending time point of the first reset signal by at least one clock cycle;
- wherein a first-stage integrator module of the plurality of integrator modules is reset by the second reset signal, and the other of the plurality of integrator modules and the feedback module are reset by the first reset signal.
Dependencies are inferred from the claim text.